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[ 302.315967] xhci_hcd 0000:04:00.0: @00000000cec3e330 00000000 00000000 00000000 00000000
[ 302.315968] xhci_hcd 0000:04:00.0: @00000000cec3e340 00000000 00000000 00000000 00000000
[ 302.315970] xhci_hcd 0000:04:00.0: @00000000cec3e350 00000000 00000000 00000000 00000000
[ 302.315971] xhci_hcd 0000:04:00.0: @00000000cec3e360 00000000 00000000 00000000 00000000
[ 302.315973] xhci_hcd 0000:04:00.0: @00000000cec3e370 00000000 00000000 00000000 00000000
[ 302.315974] xhci_hcd 0000:04:00.0: @00000000cec3e380 00000000 00000000 00000000 00000000
[ 302.315976] xhci_hcd 0000:04:00.0: @00000000cec3e390 00000000 00000000 00000000 00000000
[ 302.315977] xhci_hcd 0000:04:00.0: @00000000cec3e3a0 00000000 00000000 00000000 00000000
[ 302.315979] xhci_hcd 0000:04:00.0: @00000000cec3e3b0 00000000 00000000 00000000 00000000
[ 302.315980] xhci_hcd 0000:04:00.0: @00000000cec3e3c0 00000000 00000000 00000000 00000000
[ 302.315982] xhci_hcd 0000:04:00.0: @00000000cec3e3d0 00000000 00000000 00000000 00000000
[ 302.315983] xhci_hcd 0000:04:00.0: @00000000cec3e3e0 00000000 00000000 00000000 00000000
[ 302.315985] xhci_hcd 0000:04:00.0: @00000000cec3e3f0 cec3e000 00000000 00000000 00001802
[ 302.315986] xhci_hcd 0000:04:00.0: Ring deq = ffff8800cec3e100 (virt), 0xcec3e100 (dma)
[ 302.315987] xhci_hcd 0000:04:00.0: Ring deq updated 16 times
[ 302.315988] xhci_hcd 0000:04:00.0: Ring enq = ffff8800cec3e100 (virt), 0xcec3e100 (dma)
[ 302.315990] xhci_hcd 0000:04:00.0: Ring enq updated 16 times
[ 302.315993] xhci_hcd 0000:04:00.0: // xHC command ring deq ptr low bits + flags = @00000008
[ 302.315995] xhci_hcd 0000:04:00.0: // xHC command ring deq ptr high bits = @00000000
[ 362.475502] xhci_hcd 0000:00:14.0: Poll event ring: 4295029760
[ 362.475513] xhci_hcd 0000:00:14.0: op reg status = 0x0
[ 362.475517] xhci_hcd 0000:00:14.0: ir_set 0 pending = 0x2
[ 362.475520] xhci_hcd 0000:00:14.0: HC error bitmask = 0x4
[ 362.475522] xhci_hcd 0000:00:14.0: Event ring:
[ 362.475526] xhci_hcd 0000:00:14.0: @00000000cec0a400 cec83bb0 00000000 01000000 02038001
[ 362.475529] xhci_hcd 0000:00:14.0: @00000000cec0a410 cec83bc0 00000000 01000000 02038001
[ 362.475533] xhci_hcd 0000:00:14.0: @00000000cec0a420 cec83bd0 00000000 01000000 02038001
[ 362.475536] xhci_hcd 0000:00:14.0: @00000000cec0a430 cec83be0 00000000 01000000 02038001
[ 422.636177] xhci_hcd 0000:00:14.0: Ring deq = ffff8800cec0a0d0 (virt), 0xcec0a0d0 (dma)
[ 422.636179] xhci_hcd 0000:00:14.0: Ring deq updated 13 times
[ 422.636180] xhci_hcd 0000:00:14.0: Ring enq = ffff8800cec0a0d0 (virt), 0xcec0a0d0 (dma)
[ 422.636181] xhci_hcd 0000:00:14.0: Ring enq updated 13 times
[ 422.636184] xhci_hcd 0000:00:14.0: // xHC command ring deq ptr low bits + flags = @00000008
[ 422.636185] xhci_hcd 0000:00:14.0: // xHC command ring deq ptr high bits = @00000000
[ 422.636187] xhci_hcd 0000:00:14.0: Dev 1 endpoint ring 0:
[ 422.636583] xhci_hcd 0000:04:00.0: Poll event ring: 4295089920
[ 422.636586] xhci_hcd 0000:04:00.0: op reg status = 0x0
[ 422.636589] xhci_hcd 0000:04:00.0: ir_set 0 pending = 0x2
[ 422.636590] xhci_hcd 0000:04:00.0: HC error bitmask = 0x0
[ 422.636591] xhci_hcd 0000:04:00.0: Event ring:
[ 422.636790] xhci_hcd 0000:04:00.0: @00000000cec3e3f0 cec3e000 00000000 00000000 00001802
[ 422.636792] xhci_hcd 0000:04:00.0: Ring deq = ffff8800cec3e100 (virt), 0xcec3e100 (dma)
[ 422.636793] xhci_hcd 0000:04:00.0: Ring deq updated 16 times
[ 422.636794] xhci_hcd 0000:04:00.0: Ring enq = ffff8800cec3e100 (virt), 0xcec3e100 (dma)
[ 422.636795] xhci_hcd 0000:04:00.0: Ring enq updated 16 times
[ 422.636799] xhci_hcd 0000:04:00.0: // xHC command ring deq ptr low bits + flags = @00000008
[ 422.636801] xhci_hcd 0000:04:00.0: // xHC command ring deq ptr high bits = @00000000



