L1 cache size incorrectly reported by kernel [solved]

[Nerevar]

Using kernel 2.6.31.12:

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# cat /sys/devices/system/cpu/cpu0/cache/index1/size
64K

'dmidecode -t cache' properly reports the L1 cache size as 128K.

Is there anything that can be done short of patching the kernel to fix this?

[Shining Arcanine]

Using kernel 2.6.31.12:

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# cat /sys/devices/system/cpu/cpu0/cache/index1/size
64K

'dmidecode -t cache' properly reports the L1 cache size as 128K.

Is there anything that can be done short of patching the kernel to fix this?

What CPU do you have? If it really has a L1 cache of 128KB, then I think this is either an issue in the kernel's detection code or a semantics issue where the kernel is reporting either the data cache or the instruction cache size, rather than the combined cache size. Anyway, I am not sure if this is a serious issue, because the L1 cache is managed by hardware. Aside from reporting what size the cache is, to my knowledge, the kernel does not alter its behavior based on what size L1 cache it thinks your processor has.

[Nerevar]

My CPU: http://products.amd.com/en-na/DesktopCP ... aspx?id=66

I'm asking the question due to -march=native setting it to 64K which I'm guessing it's getting from the kernel.

Here is the command I'm running to see that -march=native is getting the wrong value:

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# gcc -### -march=native -E /usr/include/stdlib.h 2>&1 | grep "/usr/libexec/gcc/.*cc1"
 "/usr/libexec/gcc/i686-pc-linux-gnu/4.4.3/cc1" "-E" "-quiet" "/usr/include/stdlib.h" "-D_FORTIFY_SOURCE=2" "-march=k8-sse3" "-msahf" "--param" "l1-cache-size=64" "--param" "l1-cache-line-size=64" "--param" "l2-cache-size=1024" "-mtune=k8"

[Dr. Strangelove]

cat /sys/devices/system/cpu/cpu0/cache/index1/size
64K

don't forget

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cat /sys/devices/system/cpu/cpu0/cache/index0/size

# gcc -### -march=native -E /usr/include/stdlib.h 2>&1 | grep "/usr/libexec/gcc/.*cc1"
"/usr/libexec/gcc/i686-pc-linux-gnu/4.4.3/cc1" "-E" "-quiet" "/usr/include/stdlib.h" "-D_FORTIFY_SOURCE=2" "-march=k8-sse3" "-msahf" "--param" "l1-cache-size=64" "--param" "l1-cache-line-size=64" "--param" "l2-cache-size=1024" "-mtune=k8"

64 + 64 = 128

l1-cache-line-size
The size of cache line in L1 cache, in bytes.

l1-cache-size
The size of L1 cache, in kilobytes.

l2-cache-size
The size of L2 cache, in kilobytes.

http://en.wikipedia.org/wiki/CPU_cache#Details_of_operation

Hope this clears it up.

[avendesora]

GCC doesn't get the cache size from the kernel. It asks the CPU directly.

From the gcc 4.3 source, file gcc/config/driver-i386.c, function detect_caches_amd, it uses the cpuid function 0x80000005 and looks at ECX. So it only cares about the data cache size.

Your CPU has 64K L1 Data and 64K L1 Instruction cache (per core), so everything looks good.

[Nerevar]

don't forget

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cat /sys/devices/system/cpu/cpu0/cache/index0/size

It's 64K too so that's good.

# gcc -### -march=native -E /usr/include/stdlib.h 2>&1 | grep "/usr/libexec/gcc/.*cc1"
"/usr/libexec/gcc/i686-pc-linux-gnu/4.4.3/cc1" "-E" "-quiet" "/usr/include/stdlib.h" "-D_FORTIFY_SOURCE=2" "-march=k8-sse3" "-msahf" "--param" "l1-cache-size=64" "--param" "l1-cache-line-size=64" "--param" "l2-cache-size=1024" "-mtune=k8"

64 + 64 = 128

l1-cache-line-size
The size of cache line in L1 cache, in bytes.

l1-cache-size
The size of L1 cache, in kilobytes.

l2-cache-size
The size of L2 cache, in kilobytes.

Note that the cache-line-size is in bytes. So, I have 1K of 64 byte cache lines.

[Nerevar]

GCC doesn't get the cache size from the kernel. It asks the CPU directly.

From the gcc 4.3 source, file gcc/config/driver-i386.c, function detect_caches_amd, it uses the cpuid function 0x80000005 and looks at ECX. So it only cares about the data cache size.

Your CPU has 64K L1 Data and 64K L1 Instruction cache (per core), so everything looks good.

Thank you! That's what I was hoping to hear. Marking solved.

[ryszardzonk]

I have bought new shining i3-530 2.93MHz and would love to optimize it for optimal performance. I have used shinny new Gentoo Minimal 2010 08 19 stage3 and used below line to check GCC findings

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# gcc -### -march=native -E /usr/include/stdlib.h 2>&1 | grep "/usr/libexec/gcc/.*cc1"

and come out with following answer

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"-march=core2" "-mcx16" "-msahf" "-mpopcnt" "-msse4.2" "--param" "l1-cache-size=32" "--param" "l1-cache-line-size=64" "--param" "l2-cache-size=256" "-mtune=core2"

Now my questions are

1. http://download.intel.com/design/proces ... 322909.pdf Page 11 of proc spec says that

•Two cores
•A 32-KB instruction and 32-KB data first-level cache (L1) for each core
•A 256-KB shared instruction/data second-level cache (L2) for each core
•Up to 4-MB shared instruction/data third-level cache (L3), shared among all cores

Should I therefore change l1-cache-line-size to 32 or l1-cache-size to 64.

2. Is there any way to set L3 chache size as well for that CPU?

3. Why GCC 4.4.3 that comes with that stage enables -mpopcnt while according to http://gcc.gnu.org/gcc-4.5/changes.html GCC manual it is feature set only by gcc 4.5. Has it been backported from never version? Docs for http://gcc.gnu.org/gcc-4.4/changes.html GCC 4.4 do not mention it

[avendesora]

...
Should I therefore change l1-cache-line-size to 32 or l1-cache-size to 64.

Do not touch cache-line-size at all, that's how many bytes are in a cache line, irrespective of its size.
Each core has 32k L1, so the cache-size is ok too. (GCC seems to care only about l1 data cache.)

2. Is there any way to set L3 chache size as well for that CPU?

Doesn't seem to be one in the GCC man page.

3. Why GCC 4.4.3 that comes with that stage enables -mpopcnt while according to http://gcc.gnu.org/gcc-4.5/changes.html GCC manual it is feature set only by gcc 4.5. Has it been backported from never version? Docs for http://gcc.gnu.org/gcc-4.4/changes.html GCC 4.4 do not mention it

No idea. Probably.


In any case, don't try and use fancy CFLAGS. Stay with sane defaults and all will be well.

[ryszardzonk]

...
Should I therefore change l1-cache-line-size to 32 or l1-cache-size to 64.

Do not touch cache-line-size at all, that's how many bytes are in a cache line, irrespective of its size.
Each core has 32k L1, so the cache-size is ok too. (GCC seems to care only about l1 data cache.)

Now I see where it is coming from.It is just that the example for K8 cpu in the thread made me believe that it should be 32 + 32 just like 64 + 64 there was there for it which totaled at 128

Thanks for fast response