Making full use of cpu registers in CFLAGS

Message

TheCoop · Post by **TheCoop** » Tue Mar 25, 2003 12:20 pm

It may suprise you, but -march=<cpu> does not turn on support for 3dnow,mmx, sse or sse2 even if your cpu supports it

Firstly, to check what registers your cpu does support just do a 'cat /proc/cpuinfo' and look for the 'flags:' line, anything your cpu support will be in there, inc mmx, 3dnow and sse/2

Next, to alter your CFLAGS to use those registers:

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-mmmx -m3dnow -msse -msse2

(delete any your cpu doesnt support)
If youve got sse support you can also add '-mfpmath=sse,387' so the maths uses both the sse and normal coprocessor registers, effectively doubling your math throughput.

This will result in much faster programs as well as more effective use of the cpu.

charlieg · Post by **charlieg** » Tue Mar 25, 2003 1:08 pm

Can anybody testify as to the stability of this?

Plus, is this try of all flags that appear under cat /proc/cpuinfo?

You can use mine as an example.

Flags only:

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# cat /proc/cpuinfo
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 mmx fxsr sse

Full output:

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# cat /proc/cpuinfo
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 8
model name      : Celeron (Coppermine)
stepping        : 6
cpu MHz         : 728.292
cache size      : 128 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 2
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 mmx fxsr sse
bogomips        : 1433.60

charlieg · Post by **charlieg** » Tue Mar 25, 2003 1:15 pm

TheCoop wrote:It may suprise you, but -march=<cpu> does not turn on support for 3dnow,mmx, sse or sse2 even if your cpu supports it

The freehackers.org gccflags faq has more info, although I can't work out whether it agrees or disagrees with TheCoop's statement.

ZuNBiD · Post by **ZuNBiD** » Tue Mar 25, 2003 1:20 pm

... and where do I alter my CFLAGS ??

Beekster · Post by **Beekster** » Tue Mar 25, 2003 2:07 pm

You can set your CFLAGS in /etc/make.conf

from my /etc/make.conf
CFLAGS="-march=pentium4 -O3 -pipe -mmmx -msse -msse2 -fomit-frame-pointer"

TheCoop · Post by **TheCoop** » Tue Mar 25, 2003 2:43 pm

you can check for yourself by verbosly compiling a very small empty c program, which lists all the flags used. It has the -march but it doesnt list -mmmx -m3dnow or -msse

I know its somewhere in the forums, try searching for 'gcc flags' or something, ill have a more thourough look when I get home

my cflags are

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march=athlon-xp -O3 -pipe -fomit-frame-pointer -ffast-math -mmmx -m3dnow -msse -mfpmath=sse,387

and ive had no problems at all, rock solid stable even with a barton overclocked 2500+ -> 2800+

Beekster · Post by **Beekster** » Tue Mar 25, 2003 3:18 pm

Just a warning that "man gcc" states:

sse,387
Attempt to utilize both instruction sets at once. This effectivly double the amount of available registers and on chips with separate execution units for 387 and SSE the execution resources too. Use this option with care, as it is still experimental, because gcc register allocator does not model separate functional units well resulting in instable performance.

I'm not saying it's unstable, just letting people know it is not claimed to be stable...

Sounds like it could give good gains. Anyone else running with "-mfpmath=sse,387"?

chadders · Post by **chadders** » Wed Mar 26, 2003 6:46 pm

I compile with these CFLAGS and it works great for me:

CFLAGS="-march=pentium4 -O3 -pipe -mmmx -msse -msse2 -mfpmath=sse -pipe -fomit-frame-pointer -fthread-jumps -fforce-addr -frerun-cse-after-loop -frerun-loop-opt -fexpensive-optimizations -falign-functions=4 -falign-jumps=4"

Chad

lotusvale · Post by **lotusvale** » Thu Mar 27, 2003 12:18 am

does athlon tbird 1.4 support sse, sse2?
(i know it supports 3dnow and mmx.)
thx

Malakin · Post by **Malakin** » Thu Mar 27, 2003 12:32 am

does athlon tbird 1.4 support sse, sse2?

"cat /proc/cpuinfo" to see what's supported. AMD cpu's don't support sse until Athlon-xp/Duron morgan(1ghz+). No AMD cpu's currently available support sse2.

kappax · Post by **kappax** » Thu Mar 27, 2003 1:19 am

Malakin wrote:
does athlon tbird 1.4 support sse, sse2?
"cat /proc/cpuinfo" to see what's supported. AMD cpu's don't support sse until Athlon-xp/Duron morgan(1ghz+). No AMD cpu's currently available support sse2.

xp2400's last i check support sse2

lotusvale · Post by **lotusvale** » Thu Mar 27, 2003 1:51 am

thx.

shadowrider@localhost shadowrider $ cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 6
model : 4
model name : AMD Athlon(tm) processor
stepping : 4
cpu MHz : 1201.492
cache size : 256 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 mmx fxsr syscall mmxext 3dnowext 3dnow
bogomips : 2398.61

so for my tbird 1.4, would this setup be the fastest and best?
(i've read that O3 made the binaries bigger, and also it's slower at the end especially loading up the programs)

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CFLAGS="-march=athlon-tbird -O2 -pipe -mmmx -m3dnow -fomit-frame-pointer -frerun-cse-after-loop -frerun-loop-opt -fexpensive-optimizations -falign-functions=4 -ffast-math -mfpmath=sse,387

or if anybody has a better setup?

Malakin · Post by **Malakin** » Thu Mar 27, 2003 3:41 am

xp2400's last i check support sse2

Tomshardware - "SSE code is still accepted - but SSE2 is not."
http://www.tomshardware.com/cpu/20030210/barton-02.html

kappax · Post by **kappax** » Thu Mar 27, 2003 3:46 am

Malakin wrote:
xp2400's last i check support sse2
Tomshardware - "SSE code is still accepted - but SSE2 is not."
http://www.tomshardware.com/cpu/20030210/barton-02.html

I am not too sure where Mr. tom gets his info rom. but you can gert some XP2400+'s with sse2 support, i know servel ppl that have them enabled, and have the bioses that support it on the k7s5a

check out the sis section and ocworkbench.com

Malakin · Post by **Malakin** » Thu Mar 27, 2003 3:58 am

I am not too sure where Mr. tom gets his info rom. but you can gert some XP2400+'s with sse2 support, i know servel ppl that have them enabled, and have the bioses that support it on the k7s5a

You're likely confusing this with plain sse support. Do a search for "sse2 barton" on google and you can read lots of reviews etc that mention the Barton doesn't have sse2 support. There have been no significant instruction set changes to the Athlon since the Palomino. sse2 support from AMD won't be seen until hammer.

kappax · Post by **kappax** » Thu Mar 27, 2003 4:11 am

Malakin wrote:
I am not too sure where Mr. tom gets his info rom. but you can gert some XP2400+'s with sse2 support, i know servel ppl that have them enabled, and have the bioses that support it on the k7s5a
You're likely confusing this with plain sse support. Do a search for "sse2 barton" on google and you can read lots of reviews etc that mention the Barton doesn't have sse2 support. There have been no significant instruction set changes to the Athlon since the Palomino. sse2 support from AMD won't be seen until hammer.

gaahh, i am getting confized ( i was at school so i could not look in my book marks :/ o well :/

Vazagi · Post by **Vazagi** » Thu Mar 27, 2003 4:56 pm

It may suprise you, but -march=<cpu> does not turn on support for 3dnow,mmx, sse or sse2 even if your cpu supports it.

I'm getting curious. How can it be that the '-mno-sse2' flag fixes problems with '-march=pentium4' using GCC 3.2.2, if '-march=<cpu-type>' doesn't enable these flags in the first place? The '-mno-sse2' fix seems to indicate that '-march=<cpu-type>' does enable these flags. =/

jesterspet · Post by **jesterspet** » Fri Mar 28, 2003 4:32 am

Vazagi wrote:I'm getting curious. How can it be that the '-mno-sse2' flag fixes problems with '-march=pentium4' using GCC 3.2.2, if '-march=<cpu-type>' doesn't enable these flags in the first place? The '-mno-sse2' fix seems to indicate that '-march=<cpu-type>' does enable these flags. =/

Even though '-march=<cpu-type>' does not enable the sse2 flags, other optimisations can enable them when used in conjunctoin with '-march=<cpu-type>'. Exactly what those 'other optimisations' are is beyond me. I think you would have to play around with them to figure out what they are.

I used these flags and have had no problems* with GCC 3.2.2:

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CFLAGS="-s -march=pentium4 -mmmx -msse -msse2 -Os -fomit-frame-pointer -pipe -fexpensive-optimizations -fpic -frerun-cse-after-loop -frerun-loop-opt -foptimize-register-move -masm=intel"

* This includes the bug addresed here

vikwiz · Post by **vikwiz** » Fri Mar 28, 2003 10:13 am

jesterspet wrote:I used these flags and have had no problems* with GCC 3.2.2:
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CFLAGS="-s -march=pentium4 -mmmx -msse -msse2 -Os -fomit-frame-pointer -pipe -fexpensive-optimizations -fpic -frerun-cse-after-loop -frerun-loop-opt -foptimize-register-move -masm=intel"
* This includes the bug addresed here

Are you *very* sure of this? Did you try that python int conversion stuff also?
I did compile a gentoo tree with -march=pentium4, and at the finish I saw that thread, tried the 'int' code, and it really fails. I didn't give a try to boot with this tree so. What makes the difference for you? All the other flags? I did only '-march=pentium4 -O2 -pipe'.

cerri · Post by **cerri** » Sat Mar 29, 2003 1:02 pm

There are a lot of people asking "which is the best setup for XYZ cpu?". So, why not post the best setup indexed by cpu?

IE: Pentium III (M) =
CFLAGS="-march=pentium3 -O3 -pipe -fomit-frame-pointeri -fforce-addr -falign-functions=4 -fprefetch-loop-arrays"

Anyway, as reported by freehackers.org, -march=pentium3 implies -mmmx -msse...

tempy · Post by **tempy** » Sun Mar 30, 2003 7:42 pm

Okay, the source of the confusion seems to be that -march enables some CPU defines (e.g. -D__SSE__ -D__MMX__ -D__3dNOW__ -D__3dNOW_A__) but does not tell GCC to actually generate its own SSE, MMX or 3DNow assembly.

What's odd is that when you specify -mmmx or any of the other CPU features, gcc -v -Q decides you are actually requesting "-mmmx -mno-mmx" at the same time. Neither is present without it, and I don't know which takes precedence. :/

-mfpmath=sse doesn't override itself, but it may require -mno-80387 to actually work.

My CPU is an Athlon XP 1700+ and my default cflags are "-march=athlon-xp -O2 -ggdb -pipe". Short and to the point.

link97381 · Post by **link97381** » Mon Mar 31, 2003 4:16 pm

Ahhh man now I'm gonna have to recompile EVERYTHING!!! I have Dual Athlon XP's so should I set mine to

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march=athlon-xp -O3 -pipe -fomit-frame-pointer -ffast-math -mmmx -m3dnow -msse -mfpmath=sse,387

or do you have any other suggestions?

TheCoop · Post by **TheCoop** » Mon Mar 31, 2003 4:28 pm

At last!

to check which cflags are implied by certain options, create an empty.c:

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main() {}

and run:

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gcc -v -Q empty.c <options>

, and all the cflags passed are in the output

with no options you get:

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*snip*
GNU C version 3.2.2 20030322 (Gentoo Linux 1.4 3.2.2-r2) (i686-pc-linux-gnu)
        compiled by GNU C version 3.2.2 20030322 (Gentoo Linux 1.4 3.2.2-r2).
options passed:  -lang-c -v -D__GNUC__=3 -D__GNUC_MINOR__=2
 -D__GNUC_PATCHLEVEL__=2 -D__GXX_ABI_VERSION=102 -D__ELF__ -Dunix
 -D__gnu_linux__ -Dlinux -D__ELF__ -D__unix__ -D__gnu_linux__ -D__linux__
 -D__unix -D__linux -Asystem=posix -D__NO_INLINE__ -D__STDC_HOSTED__=1
 -Acpu=i386 -Amachine=i386 -Di386 -D__i386 -D__i386__ -D__tune_i686__
 -D__tune_pentiumpro__
options enabled:  -fpeephole -ffunction-cse -fkeep-static-consts
 -fpcc-struct-return -fgcse-lm -fgcse-sm -fsched-interblock -fsched-spec
 -fbranch-count-reg -fcommon -fgnu-linker -fargument-alias -fident
 -fmath-errno -ftrapping-math -m80387 -mhard-float -mno-soft-float
 -mieee-fp -mfp-ret-in-387 -mcpu=pentiumpro -march=i386
*snip*

and with -march=athlon-xp added you get:

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*snip*
GNU C version 3.2.2 20030322 (Gentoo Linux 1.4 3.2.2-r2) (i686-pc-linux-gnu)
        compiled by GNU C version 3.2.2 20030322 (Gentoo Linux 1.4 3.2.2-r2).
options passed:  -lang-c -v -D__GNUC__=3 -D__GNUC_MINOR__=2
 -D__GNUC_PATCHLEVEL__=2 -D__GXX_ABI_VERSION=102 -D__ELF__ -Dunix
 -D__gnu_linux__ -Dlinux -D__ELF__ -D__unix__ -D__gnu_linux__ -D__linux__
 -D__unix -D__linux -Asystem=posix -D__NO_INLINE__ -D__STDC_HOSTED__=1
 -Acpu=i386 -Amachine=i386 -Di386 -D__i386 -D__i386__ -D__athlon
 -D__athlon__ -D__athlon_sse__ -D__tune_athlon__ -D__tune_athlon_sse__
 -D__SSE__ -D__MMX__ -D__3dNOW__ -D__3dNOW_A__ -march=athlon-xp
options enabled:  -fpeephole -ffunction-cse -fkeep-static-consts
 -fpcc-struct-return -fgcse-lm -fgcse-sm -fsched-interblock -fsched-spec
 -fbranch-count-reg -fcommon -fgnu-linker -fargument-alias -fident
 -fmath-errno -ftrapping-math -m80387 -mhard-float -mno-soft-float
 -mieee-fp -mfp-ret-in-387 -mcpu=athlon-xp -march=athlon-xp
*snip*

Note the lack of any -mmmx, -m3dnow or -msse

wharper · Post by **wharper** » Tue Apr 01, 2003 3:16 am

hmm, it seems that gcc set's the optimizations correctly within the compiler?

This is a snippet from: http://www.freehackers.org/gentoo/gccflags/faq.html
I have not looked at the source but this seems correct. This is also why you did not see the compiler flags on the command line when looking at the compiled binary.

In the gcc source, have a look at the file gcc-3.2/gcc/config/i386/i386.c Here's an excerpt :

Options implied by -march=

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const processor_alias_table[] =
    {
      {"i386", PROCESSOR_I386, 0},
      {"i486", PROCESSOR_I486, 0},
      {"i586", PROCESSOR_PENTIUM, 0},
      {"pentium", PROCESSOR_PENTIUM, 0},
      {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
      {"i686", PROCESSOR_PENTIUMPRO, 0},
      {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
      {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
      {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
      {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2 |
                                       PTA_MMX | PTA_PREFETCH_SSE},
      {"k6", PROCESSOR_K6, PTA_MMX},
      {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
      {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
      {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
                                   | PTA_3DNOW_A},
      {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
                                         | PTA_3DNOW | PTA_3DNOW_A},
      {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
                                    | PTA_3DNOW_A | PTA_SSE},
      {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
                                      | PTA_3DNOW_A | PTA_SSE},
      {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
                                      | PTA_3DNOW_A | PTA_SSE},
    };

It also seems that -O3 does all of the other nifty flags as well?

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 if (optimize >= 1)
    {
      flag_defer_pop = 1;
      flag_thread_jumps = 1;
#ifdef DELAY_SLOTS
      flag_delayed_branch = 1;
#endif
#ifdef CAN_DEBUG_WITHOUT_FP
      flag_omit_frame_pointer = 1;
#endif
      flag_guess_branch_prob = 1;
      flag_cprop_registers = 1;
    }

  if (optimize >= 2)
    {
      flag_optimize_sibling_calls = 1;
      flag_cse_follow_jumps = 1;
      flag_cse_skip_blocks = 1;
      flag_gcse = 1;
      flag_expensive_optimizations = 1;
      flag_strength_reduce = 1;
      flag_rerun_cse_after_loop = 1;
      flag_rerun_loop_opt = 1;
      flag_caller_saves = 1;
      flag_force_mem = 1;
      flag_peephole2 = 1;
#ifdef INSN_SCHEDULING
      flag_schedule_insns = 1;
      flag_schedule_insns_after_reload = 1;
#endif
      flag_regmove = 1;
      flag_strict_aliasing = 1;
      flag_delete_null_pointer_checks = 1;
      flag_reorder_blocks = 1;
    }

  if (optimize >= 3)
    {
      flag_inline_functions = 1;
      flag_rename_registers = 1;
    }

my .02

janderson · Post by **janderson** » Tue Apr 01, 2003 6:12 am

jesterspet wrote: I used these flags and have had no problems* with GCC 3.2.2:
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CFLAGS="-s -march=pentium4 -mmmx -msse -msse2 -Os -fomit-frame-pointer -pipe -fexpensive-optimizations -fpic -frerun-cse-after-loop -frerun-loop-opt -foptimize-register-move -masm=intel"

Seems you've gone to some trouble to optimize for speed, but you may be incurring some not-so-good penalties by using -Os. I believe -Os causes certain data types, functions and perhaps some other things to be misaligned to make the binary smaller. The misalignment will mean that you take a significant performance hit when fetching misaligned data. Since you probably have a good chunk of memory and a fast CPU, you probably don't want to use -Os.

Cheers,

jon

Making full use of cpu registers in CFLAGS

Making full use of cpu registers in CFLAGS

Hmm

Re: Making full use of cpu registers in CFLAGS