Hyper-Threading?

Message

kongit · Post by **kongit** » Wed Mar 31, 2004 9:29 pm

I bought a dell inspiron 5100 with a pentium4 2.4 ghz processor near the end of last summer. Nowhere does it say anything about it being able to support hyper-threading. However one day I was looking though my proc directory and cat cpuinfo and in the flags was a mysterious ht. At first I was puzzled but finally I decided to figure out exactly what was going on. So I emerged x86info and ran it with -a and here is its output:

x86info v1.11. Dave Jones 2001, 2002
Feedback to <davej@suse.de>.

Found 1 CPU
eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
eax in: 0x00000001, eax = 00000f27 ebx = 00010809 ecx = 00004400 edx = bfebf9ff
eax in: 0x00000002, eax = 665b5101 ebx = 00000000 ecx = 00000000 edx = 007b7040

eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000002, eax = 20202020 ebx = 20202020 ecx = 20202020 edx = 6e492020
eax in: 0x80000003, eax = 286c6574 ebx = 50202952 ecx = 69746e65 edx = 52286d75
eax in: 0x80000004, eax = 20342029 ebx = 20555043 ecx = 30342e32 edx = 007a4847

Family: 15 Model: 2 Stepping: 7 Type: 0
CPU Model: Pentium 4 Xeon (Northwood) [C1] Original OEM
Processor name string: Intel(R) Pentium(R) 4 CPU 2.40GHz

Feature flags:
Onboard FPU
Virtual Mode Extensions
Debugging Extensions
Page Size Extensions
Time Stamp Counter
Model-Specific Registers
Physical Address Extensions
Machine Check Architecture
CMPXCHG8 instruction
SYSENTER/SYSEXIT
Memory Type Range Registers
Page Global Enable
Machine Check Architecture
CMOV instruction
Page Attribute Table
36-bit PSEs
CLFLUSH instruction
Debug Trace Store
ACPI via MSR
MMX support
FXSAVE and FXRESTORE instructions
SSE support
SSE2 support
CPU self snoop
Hyper-Threading
Automatic clock Control
Pending Break Enable

Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 128 entries.
Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
L1 Data cache:
Size: 8KB Sectored, 4-way associative.
line size=64 bytes.
No L3 cache
Instruction trace cache:
Size: 12K uOps 8-way associative.
L2 unified cache:
Size: 512KB Sectored, 8-way associative.
line size=64 bytes.

Number of logical processors supported within the physical package: 1

Connector type: Socket478 (PGA478 Socket)

Datasheet: http://developer.intel.com/design/penti ... 988703.pdf
http://developer.intel.com/design/penti ... 864304.pdf
Errata: http://developer.intel.com/design/penti ... 919928.pdf

MTRR registers:
MTRRcap (0xfe): MTRRphysBase0 (0x200): MTRRphysMask0 (0x201): MTRRphysBase1 (0x202): MTRRphysMask1 (0x203): MTRRphysBase2 (0x204): MTRRphysMask2 (0x205): MTRRphysBase3 (0x206): MTRRphysMask3 (0x207): MTRRphysBase4 (0x208): MTRRphysMask4 (0x209): MTRRphysBase5 (0x20a): MTRRphysMask5 (0x20b): MTRRphysBase6 (0x20c): MTRRphysMask6 (0x20d): MTRRphysBase7 (0x20e): MTRRphysMask7 (0x20f): MTRRfix64K_00000 (0x250): MTRRfix16K_80000 (0x258): MTRRfix16K_A0000 (0x259): MTRRfix4K_C8000 (0x269): MTRRfix4K_D0000 0x26a: MTRRfix4K_D8000 0x26b: MTRRfix4K_E0000 0x26c: MTRRfix4K_E8000 0x26d: MTRRfix4K_F0000 0x26e: MTRRfix4K_F8000 0x26f: MTRRdefType (0x2ff):

2392.04 MHz processor (estimate).

What exactly does this mean?

klarnox · Post by **klarnox** » Wed Mar 31, 2004 9:35 pm

I seem to recall one or two other threads discussing this and the conclusion was that all of these faster P4 CPUs showed the ht flag, seeming to indicated that hyperthreading was possible, however it ended up that it is disabled on the CPU.

kongit · Post by **kongit** » Wed Mar 31, 2004 9:43 pm

hmm. I probably got my hopes up for nothing. Do you think that trying out two of the same kernel one with smp enabled and the other not would show a noticeable difference if the processor did have ht?

jtaylor72 · Post by **jtaylor72** » Wed Mar 31, 2004 9:46 pm

kongit wrote:hmm. I probably got my hopes up for nothing. Do you think that trying out two of the same kernel one with smp enabled and the other not would show a noticeable difference if the processor did have ht?

I think your BIOS would tell you if you had HT or not. I would guess the BIOS would have to recognize it for the OS to recognize it.

kongit · Post by **kongit** » Wed Mar 31, 2004 9:55 pm

I think your BIOS would tell you if you had HT or not. I would guess the BIOS would have to recognize it for the OS to recognize it.

good point I will check it.

Gatak · Post by **Gatak** » Wed Mar 31, 2004 10:06 pm

Is it not enough to enable SMP support?

kongit · Post by **kongit** » Wed Mar 31, 2004 10:18 pm

I don't think my bios supports it so

ewan.paton · Post by **ewan.paton** » Thu Apr 01, 2004 3:07 am

bad luck but all p4 core chips suport HT its just that intel cut the conections so they could sell it as a feature on xeon chips, much like all the prescot cpus (p4c chips) have amd64 compatible regisers(part of the reason why they are so hot) but disabled at the factory.
try an smp if you want and play with the bios but i doubt you will have any luck