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CaptainBlood
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 Posted: Fri Oct 02, 2020 8:56 am Post subject: x2apic benefits... |
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Here's a 4 Gb RAM+Skylake-2-cores.
Only qemu for arm64.
kernel IOMMU activated as security measure.
It has unhide x2apic kernel option.
Any benefit activating it?
Thks 4 ur attention, interest & support. |
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CaptainBlood
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| Posted: Sat Oct 03, 2020 7:01 am Post subject: |
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Intel specs
I'ven't read it enough times to make up my mind.
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ff11
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| Posted: Sat Oct 03, 2020 10:15 am Post subject: |
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When enabled, processor x2APIC support helps operating systems run more efficiently on high core count configurations and optimizes interrupt distribution in virtualized environments.
You have one "Skylake-2-cores", so maybe you want it disabled.
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CaptainBlood
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| Posted: Sat Oct 03, 2020 10:38 am Post subject: |
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Sure  . There's also: | Code: | • More efficient MSR interface to access APIC registers.
— To enhance inter-processor and self directed interrupt delivery as well as the
ability to virtualize the local APIC, the APIC register set can be accessed only
through MSR based interfaces in the x2APIC mode. The Memory Mapped IO
(MMIO) interface used by xAPIC is not supported in the x2APIC mode. |
which I don't fully understand  : | Code: | - enhance inter-processor and self directed interrupt delivery (?faster)
- virtualize the local APIC (?safer)
- MMIO interface used by xAPIC is not supported (?critical) |
Thks 5 ur attention, interest & support. |
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ff11
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Joined: 10 Mar 2014
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| Posted: Sat Oct 03, 2020 10:57 am Post subject: |
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| CaptainBlood wrote: | Sure . There's also: | Code: | • More efficient MSR interface to access APIC registers.
— To enhance inter-processor and self directed interrupt delivery as well as the
ability to virtualize the local APIC, the APIC register set can be accessed only
through MSR based interfaces in the x2APIC mode. The Memory Mapped IO
(MMIO) interface used by xAPIC is not supported in the x2APIC mode. |
which I don't fully understand : | Code: | - enhance inter-processor and self directed interrupt delivery (?faster)
- virtualize the local APIC (?safer)
- MMIO interface used by xAPIC is not supported (?critical) |
Thks 5 ur attention, interest & support. |
Yep! It can be useful if you want to have many visualized environments running at the same time, but I'm guessing you don't wanna do this on a 2-core processor.
The Advanced Programmable Interrupt Controller (APIC) is intended to solve interrupt routing efficiency issues in multiprocessor computer systems. I don't see this being a issue on a 2-core system. Simpler routing can be faster, as it doesn't carry the extra controller's code that can control many ones.
But, again, if one day you want to run more than 10 virtual machines at the same time on this processor, go ahead, enable and test, as it can be useful. It's hard to be precise on the exact number of cores that this feature pays off for the extra code.
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Anon-E-moose
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Joined: 23 May 2008
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| Posted: Sat Oct 03, 2020 11:56 am Post subject: |
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| Quote: | The xAPIC was introduced with the Pentium 4, while the x2APIC is the most recent generation of the Intel's programmable interrupt controller, introduced with the Nehalem microarchitecture in November 2008.[17] The major improvements of the x2APIC address the number of supported CPUs and performance of the interface.
The x2APIC now uses 32 bits to address CPUs, allowing to address up to 232 − 1 CPUs using the physical destination mode. The logical destination mode now works differently and introduces clusters; using this mode, one can address up to 220 − 16 processors. The x2APIC architecture also provides backward compatibility modes to the original Intel APIC Architecture (introduced with the Pentium/P6) and with the xAPIC architecture (introduced with the Pentium 4).
The improved interface reduces the number of needed APIC register access for sending Inter-processor interrupts (IPIs). Because of this advantage, KVM can and does emulate the x2APIC for older processors that do not physically support it, and this support is exposed from QEMU going back to Conroe and even for AMD Opteron G-series processors (neither of which natively support x2APIC).[18][19] |
https://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller#X2APIC
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UM780 xtx, 6.14 zen kernel, gcc 15, openrc, wayland
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ff11
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Anon-E-moose
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| Posted: Sat Oct 03, 2020 1:58 pm Post subject: |
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The important part is this The major improvements of the x2APIC address the number of supported CPUs and performance of the interface.
which kind of addresses the original query, Any benefit activating it?
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ff11
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| Posted: Sat Oct 03, 2020 2:14 pm Post subject: |
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| Anon-E-moose wrote: | The important part is this The major improvements of the x2APIC address the number of supported CPUs and performance of the interface.
... |
that, by the way, for the number is more than 255 cores/threads, and for the performance should be more than 10 cores/threads. Even the CONFIG_X86_X2APIC help have "This allows 32-bit apic IDs (so it can support very large systems), and accesses the local apic via MSRs not via mmio.". And that second point, of using MSRs, shouldn't affect performance with less than 10 core/threads so much (to be fair, we would need a reliable benchmark to confirm it).
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* AlphaGo - The Movie - Full Documentary "I want to apologize for being so powerless" - Lee |
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Kernel & Hardware
