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dE_logics
Advocate
Joined: 02 Jan 2009
Posts: 2253
Location: $TERM
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 Posted: Tue Apr 01, 2014 10:30 am Post subject: GCC chooses wrong -march=native flags? |
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I got an old AMD Athlon 64 processor --
| Code: | processor : 0
vendor_id : AuthenticAMD
cpu family : 15
model : 47
model name : AMD Athlon(tm) 64 Processor 3000+
stepping : 2
cpu MHz : 1808.059
cache size : 512 KB
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt lm 3dnowext 3dnow up rep_good nopl pni lahf_lm
bogomips : 3616.11
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp tm stc |
As you can see it does not support anything above sse2, however --
| Code: | gcc -march=native -E -v - </dev/null 2>&1 | grep cc1
/usr/libexec/gcc/x86_64-pc-linux-gnu/4.8.2/cc1 -E -quiet -v - -march=[b]k8-sse3[/b] -mno-cx16 -msahf -mno-movbe -mno-aes -mno-pclmul -mno-popcnt -mno-abm -mno-lwp -mno-fma -mno-fma4 -mno-xop -mno-bmi -mno-bmi2 -mno-tbm [b]-mno-avx -mno-avx2 -mno-sse4.2 -mno-sse4.1[/b] -mno-lzcnt -mno-rtm -mno-hle -mno-rdrnd -mno-f16c -mno-fsgsbase -mno-rdseed -mno-prfchw -mno-adx -mfxsr -mno-xsave -mno-xsaveopt --param l1-cache-size=64 --param l1-cache-line-size=64 --param l2-cache-size=512 -mtune=k8 |
using gcc 4.8.2
And using Debian's GCC 4.7.2 I get similar output.
Is this something I should be worried of?
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Anon-E-moose
Watchman
Joined: 23 May 2008
Posts: 6097
Location: Dallas area
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| Posted: Tue Apr 01, 2014 10:54 am Post subject: |
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I wouldn't think that there would be a problem.
In a cursory google search I ran across this.
| Quote: | ONe fo my machines still has K8 - AMD64 X2 6000+ in it.
cat /proc/cpuinfo doesn't list SSE3 capabilities of the CPU, whereas AMD
states that newer AMD64 (2005 and after that) are SSE3 capable and
gcc-4.3.2 has -march=k8-sse3
Wikipedia states that AMD K8 is SSE3 capable, except for a few
Intel-specific instructions. Maybe that is the reason why it isn't
listed in /proc/cpuinfo ?
Until now I have always used -march=k8, but now I wonder whether it
would be safe to use k8-sse3.
Has anyone tried this yet ? |
and this reply
| Quote: | SSE3 capability is listed as "pni" (Prescott New Instructions) in
/proc/cpuinfo flags. I've been using SSE3 with my AMD64 X2 4600+ for 3
years now. |
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dE_logics
Advocate
Joined: 02 Jan 2009
Posts: 2253
Location: $TERM
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| Posted: Tue Apr 01, 2014 11:17 am Post subject: |
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Humm.
Ok. Thanks!
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megabaks
Apprentice
Joined: 22 Jan 2012
Posts: 253
Location: Russia && Saint-Petersburg
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| Posted: Tue Apr 01, 2014 2:20 pm Post subject: |
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| Code: | | echo "int main() { return 0; }" |LANG=en gcc -march=k8-sse3 -v -Q -x c - 2>&1 | awk -F ":" '/^ -/ {print $1}' | tr " " "\n" | sort | uniq |
output | Code: | -fasynchronous-unwind-tables
-fauto-inc-dec
-fbranch-count-reg
-fcommon
-fdelete-null-pointer-checks
-fdwarf2-cfi-asm
-fearly-inlining
-feliminate-unused-debug-types
-ffunction-cse
-fgcse-lm
-fgnu-runtime
-fident
-finline-atomics
-fira-hoist-pressure
-fira-share-save-slots
-fira-share-spill-slots
-fivopts
-fkeep-static-consts
-fleading-underscore
-fmath-errno
-fmerge-debug-strings
-fmove-loop-invariants
-fpcc-struct-return
-fpeephole
-fprefetch-loop-arrays
-fsched-critical-path-heuristic
-fsched-dep-count-heuristic
-fsched-group-heuristic
-fsched-interblock
-fsched-last-insn-heuristic
-fsched-rank-heuristic
-fsched-spec
-fsched-spec-insn-heuristic
-fsched-stalled-insns-dep
-fshow-column
-fsigned-zeros
-fsplit-ivs-in-unroller
-fstrict-volatile-bitfields
-fsync-libcalls
-ftrapping-math
-ftree-coalesce-vars
-ftree-cselim
-ftree-forwprop
-ftree-loop-if-convert
-ftree-loop-im
-ftree-loop-ivcanon
-ftree-loop-optimize
-ftree-parallelize-loops=
-ftree-phiprop
-ftree-pta
-ftree-reassoc
-ftree-scev-cprop
-ftree-slp-vectorize
-ftree-vect-loop-version
-funit-at-a-time
-funwind-tables
-fvar-tracking
-fvar-tracking-assignments
-fzero-initialized-in-bss
-m32
-m3dnow
-m80387
-m96bit-long-double
-maccumulate-outgoing-args
-malign-stringops
-mfancy-math-387
-mfp-ret-in-387
-mfxsr
-mglibc
-mieee-fp
-mlong-double-80
-mmmx
-mno-red-zone
-mno-sse4
-mprfchw
-mpush-args
-msahf
-msse
-msse2
-msse3
-mtls-direct-seg-refs |
try with "native"
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xaviermiller
Bodhisattva
Joined: 23 Jul 2004
Posts: 8708
Location: ~Brussels - Belgique
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| Posted: Tue Apr 01, 2014 5:07 pm Post subject: |
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Same for me, and kl-ssse3 works really well !
| /proc/cpuinfo (1 of 2): | processor : 0
vendor_id : AuthenticAMD
cpu family : 15
model : 35
model name : AMD Athlon(tm)64 X2 Dual Core Processor 4400+
stepping : 2
microcode : 0x4d
cpu MHz : 2200.000
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt lm 3dnowext 3dnow rep_good nopl extd_apicid pni lahf_lm cmp_legacy
bogomips : 4419.96
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp |
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krinn
Watchman
Joined: 02 May 2003
Posts: 7470
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dE_logics
Advocate
Joined: 02 Jan 2009
Posts: 2253
Location: $TERM
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| Posted: Fri Apr 04, 2014 3:20 am Post subject: |
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I'm getting invalid optcode when running systemd.
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vaxbrat
l33t
Joined: 05 Oct 2005
Posts: 731
Location: DC Burbs
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| Posted: Fri Apr 04, 2014 5:42 am Post subject: Define "old" |
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| Just how old is that thing? I was looking at the list of processors in Wikipedia and the entry has no direct translation of decimal model numbers (47) like that to what they show as "steppings". It isn't until the Venice (2005) that SSE3 support was added. Other googling on (athlon 64 "model 47") results in a thread somewhere suggesting that a model 47 stepping 2 may be a Venice core, so maybe gcc was right in its analysis. |
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Navar
Guru
Joined: 20 Aug 2012
Posts: 353
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| Posted: Fri Apr 04, 2014 7:11 am Post subject: |
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| dE_logics wrote: | | I'm getting invalid optcode when running systemd. |
Why it must be all those new fangled multimedia options! Does it auto stream encode uploads to youtube now? 
Sorry, I just couldn't resist. (we really need a beverage spray emoticon because that was the display after seeing thy post) |
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dE_logics
Advocate
Joined: 02 Jan 2009
Posts: 2253
Location: $TERM
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| Posted: Sat Apr 05, 2014 3:53 am Post subject: Re: Define "old" |
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| vaxbrat wrote: | | Just how old is that thing? I was looking at the list of processors in Wikipedia and the entry has no direct translation of decimal model numbers (47) like that to what they show as "steppings". It isn't until the Venice (2005) that SSE3 support was added. Other googling on (athlon 64 "model 47") results in a thread somewhere suggesting that a model 47 stepping 2 may be a Venice core, so maybe gcc was right in its analysis. |
8-9 years old. Those AMD + Nvidia days.
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