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Randy Andy
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PostPosted: Mon Apr 01, 2013 11:52 am    Post subject: Illegal instruction when I chroot into my Atom arch. Reply with quote

Hi Folks,

the following problem treads me since a period of time I can't specifies exactly, must be during some month.

Every time, when I chroot on my Desktop PC (~x86_64 Intel(R) Core(TM)2 Quad CPU Q6600) into a local Backup of my Netbook (~i686 Intel(R) Atom(TM) CPU N270), I got an illegal instruction error.

I've done this thousand times before successfully, in the same way.
On the same machine resides some more backups of different ~x86 pentium- and athlon-systems.
To these, I can chroot successfully furthermore, to do upgrades for it into this kind of 32Bit chroot enviroment, similar to the procedure described here: http://www.gentoo.org/proj/en/base/amd64/howtos/chroot.xml

It already comes up while chrooting, when I enter this command:

Code:
env-update && source /etc/profile
illegal instruction


also on a simple ls command and quite for a emerge –info.

So what could be the root cause for these illegal instruction and how to fix it?

Has something changed to the toolchain regarding the support of the atom arch, so that I now need a native crosscompiler I never need to use before?

[Edit1]

Isn't the instruction set of my
Code:
cat /proc/cpuinfo
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 15
model name      : Intel(R) Core(TM)2 Quad CPU    Q6600  @ 2.40GHz
stepping        : 11
microcode       : 0xb3
cpu MHz         : 1600.000
cache size      : 4096 KB
physical id     : 0
siblings        : 4
core id         : 0
cpu cores       : 4
apicid          : 0
initial apicid  : 0
fpu             : yes
fpu_exception   : yes
cpuid level     : 10
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good nopl aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm lahf_lm dtherm tpr_shadow vnmi flexpriority
downwards compatible to my Atom arch, shown here:

Code:

cat /proc/cpuinfo
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 28
model name      : Intel(R) Atom(TM) CPU N270   @ 1.60GHz
stepping        : 2
microcode       : 0x212
cpu MHz         : 1600.000
cache size      : 512 KB
physical id     : 0
siblings        : 1
core id         : 0
cpu cores       : 1
apicid          : 0
initial apicid  : 0
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 10
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 xtpr pdcm movbe lahf_lm dtherm
bogomips        : 3199.73
clflush size    : 64
cache_alignment : 64
address sizes   : 32 bits physical, 32 bits virtual
power management:

If not, the illegal instruction no wonders.

[Edit2]
I've done a diff between the both, here's the result:
Code:

Following from my Quad Core are not available on the Atom:

(pat)_pse36
syscall nx lm constant_tsc arch_perfmon pebs bts rep_good nopl aperfm(perf) pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm
tpr_shadow vnmi flexpriority


Following from Atom are not available on the my Quad Core:
nx constant_tsc arch_perfmon pebs bts aperfm(perf) pni dtes64 monitor ds_cpl est tm2 ssse3 xtpr pdcm movbe

Expressions in brackets are present on both, but was named to be better readable.


On earlier times, possibly as long as everything works fine for me, I had compiled my Atom system with this CFLAGS:
Code:
-march=prescott
cause -march=atom was not an available option.
Later I switched to the improved gcc option atom. So I guess now, as longer as I'm thinking about, this must me the reason for this kind of hassle.

Nevertheless, I'm interested to proof this theory.
Next step should be to get the instruction set of the prescott (I don't hold) and to compare it with my core 2 quad for accordance.

In the meantime I found this correlating Thread and would like to use the code given here:https://forums.gentoo.org/viewtopic-t-70894.html#6822286
but I'm not that experienced to know how to compile and use it by hand.
Also I don't want to influence my packet management and so I want to do this in an uncritical and clear way to my system.

Help is very appreciated.
Andy.
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chithanh
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PostPosted: Mon Apr 01, 2013 10:53 pm    Post subject: Reply with quote

-march=atom can lead to illegal instructions on N270 too, because it is only intended for 64-bit atoms

If you want to be able to chroot from the Core2 into the Atom install, -march=prescott -mtune=atom would probably make sense.
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Randy Andy
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PostPosted: Tue Apr 02, 2013 11:36 am    Post subject: Reply with quote

Thank you chithanh.

Now I see that I've chosen the wrong settings for my CPU, what must be the root cause for my hassle.

After reading some documentation to find out the most performance settings for my CPU, I found out some more facts:

Prescott supports:
MMX, SSE, SSE2, SSE3, Intel 64, XD-Bit, Hyper-Threading

My Atom N270 supports:
MMX, SSE, SSE2, SSE3, SSSE3, XD-Bit, Hyper-Threading


The missing support for Intel 64 arch is no problem, reasons are clear to me.
But I don't use the SSSE3 instruction set on the Atom if I only using this settings -march=prescott -mtune=atom, right?

Doc told me:
"simd’
Enable Advanced SIMD instructions. This implies floating-point instructions are enabled. This is the default for all current possible values for options -march and -mcpu=."

But I guess I found out that SIMD doesn't include SSSE3 instructions, so I have to activate it for the CFLAGS additionally, right?

If so, I'm not fully sure what's the right syntax for this, cause I'm eventually misinterpret the gcc doc (I'm no native).
So is it:


a) -march=prescott -ssse3 -mtune=atom

b) -march=prescott -mtune=atom -mfpmath=ssse3

c) -march=prescott -mtune=atom -ssse3



All of the settings above should work again on my Quad Core, cause it supports them all: MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, EIST, XD-Bit, IVT


Thanks in advance, Andy.
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chithanh
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PostPosted: Tue Apr 02, 2013 11:44 am    Post subject: Reply with quote

Randy Andy wrote:
Prescott supports:
MMX, SSE, SSE2, SSE3, Intel 64, XD-Bit, Hyper-Threading
No, original Prescott did not support Intel 64, that was introduced with Nocona.
Randy Andy wrote:

a) -march=prescott -ssse3 -mtune=atom

b) -march=prescott -mtune=atom -mfpmath=ssse3

c) -march=prescott -mtune=atom -ssse3

Neither of these will work. If you want to squeeze the last bit of performance out of the system, try
Code:
-march=prescott -mssse3 -mfpmath=sse -mtune=atom
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Randy Andy
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PostPosted: Tue Apr 02, 2013 4:40 pm    Post subject: Reply with quote

[quote="chithanh"]
Randy Andy wrote:
Prescott supports:
MMX, SSE, SSE2, SSE3, Intel 64, XD-Bit, Hyper-Threading
No, original Prescott did not support Intel 64, that was introduced with Nocona.
Where did you typically research such information?
I used this site: http://de.wikipedia.org/wiki/Intel_Pentium_4#Prescott_2 but looked at Prescott only, not No.2.
Now, after reading your post, I saw that the information on the English version is different, look here: http://en.wikipedia.org/wiki/Pentium_4#Prescott


Randy Andy wrote:

a) -march=prescott -ssse3 -mtune=atom

b) -march=prescott -mtune=atom -mfpmath=ssse3

c) -march=prescott -mtune=atom -ssse3

chithanh wrote:
Neither of these will work. If you want to squeeze the last bit of performance out of the system, try
Code:
-march=prescott -mssse3 -mfpmath=sse -mtune=atom


Ah, thanks for the help, now I see where I was wrong. Now I'm using your settings while compiling my system.

By the way...
I just checked what kind of CFLAGS are recognized by the automatism of:
Code:
gcc -march=native -E -v - </dev/null 2>&1 | grep cc1
which gives me the following results:
Code:
-E -quiet -v - -march=atom -mno-cx16 -msahf -mmovbe -mno-aes -mno-pclmul -mno-popcnt -mno-abm -mno-lwp -mno-fma -mno-fma4 -mno-xop -mno-bmi -mno-tbm -mno-avx -mno-sse4.2 -mno-sse4.1 --param l1-cache-size=24 --param l1-cache-line-size=64 --param l2-cache-size=512 -mtune=atom


These results/features doesn't seem to be true, if the information from this site is right, this time. I think it is, at least for my Atom N270:
http://de.wikipedia.org/wiki/Intel_Atom#Diamondville_.28Atom-.28N.29200-_und_300-Serie.29
One example, N270 doesn't support SSE4 instruction set, but gcc's detection above told me so, if I don't misinterpret its output right.
Also confusing: It tolds me atom for both, -march and -mtune.

So it's hard to believe in any kind of information. Which one I should trust, to find the right settings. How did you find the right one?
Best regards, Andy.
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krinn
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PostPosted: Tue Apr 02, 2013 10:57 pm    Post subject: Reply with quote

1/ you should just set your cpu as gcc told you
2/ I disagree totally with the chithanh suggest that -march=atom is for 64 bits atom, until i have read some gcc doc telling that clearly.
It's an old myth that came when gcc introduce prescott and nocona push by users that were thinking you can't use nocona because of the 64bits instruction set in it.
If anyone keep following this logic, it would imply that -march=corei7 is illegal to be use in a 32bits env, because that include 64bits instruction set.
3/ your gcc is just telling you truth, look at my output
Code:
gcc -march=native -E -v - </dev/null 2>&1 | grep cc1
 /usr/libexec/gcc/i686-pc-linux-gnu/4.7.1/cc1 -E -quiet -v - -march=corei7 -mcx16 -msahf -mno-movbe -mno-aes -mno-pclmul -mpopcnt -mno-abm -mno-lwp -mno-fma -mno-fma4 -mno-xop -mno-bmi -mno-bmi2 -mno-tbm -mno-avx -mno-avx2 -msse4.2 -msse4.1 -mno-lzcnt -mno-rdrnd -mno-f16c -mno-fsgsbase --param l1-cache-size=32 --param l1-cache-line-size=64 --param l2-cache-size=8192 -mtune=corei7

-mno-anything = disable support for "anything". so -mno-sse4.1 is invert flag of -msse4.1
4/ if a cflags is imply because of your -march settings (so any cpu from this family is known to have that cflags), gcc won't tell you it will enable it, it will only show specific one that are enable or disable for your cpu.
This mean if it's known all atom handle ssse3 you won't see -mssse3 but if some cpu handle a cflags and some others from the same familly doesn't, you will see the specific -mno-cflags that disable it.
As you could have seen in the output for my cpu, if you trust that output as-is, you may then think my cpu just doesn't handle sse, as -msse -msse2... aren't shown.
you should use:
Code:
gcc -Q --help=target -march=native

and here's a partial output, showing that indeed gcc enable sse2 and sse3 but disable sse2avx as it should.
Code:
  -msse                             [enabled]
  -msse2                            [enabled]
  -msse2avx                         [disabled]
  -msse3                            [enabled]

This way you will really see what cflags are enable per default because of your atom family cpu.

Your invalid instruction may comes from per default enable cflags for atom that is bad for your core2, or it's also known some gcc 4.5 version are bug at detecting and producing proper code for some atom, core2 and corei7 family. You better upgrade your gcc to avoid it or check bugs.gentoo.org or gcc changelog to see if your version is patch for that.

As a sample, if -mmovbe is enable because of your atom arch, your core2 will drop illegal instruction with anything that use it. It means you should produce code with "-march=native -mno-movbe" to stop that.
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Randy Andy
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PostPosted: Wed Apr 03, 2013 5:40 pm    Post subject: Reply with quote

Thank you krinn,

for bringing more light into the dark.
Your comments are very helpful to me cause I did understand the gcc documentation partly in a different way.
With the help of your statements, I thought I were able to interpret the output of my gcc status information in the right way.

But when I compare your gcc lines, considering the different CPU, with mine, I'm again confused, cause the different behaviour of the output of
Code:
gcc -Q --help=target -march=native
of my Quad Core shows (only a little block as an example, sorry fo the german language, disabled=ausgeschaltet, enabled=eingeschaltet)
Code:

-msahf                                [eingeschaltet]
  -msoft-float                          [ausgeschaltet]
  -msse                                 [ausgeschaltet]
  -msse2                                [ausgeschaltet]
  -msse2avx                             [ausgeschaltet]
  -msse3                                [ausgeschaltet]
  -msse4                                [ausgeschaltet]
  -msse4.1                              [ausgeschaltet]
  -msse4.2                              [ausgeschaltet]
  -msse4a                               [ausgeschaltet]
  -msse5                     
  -msseregparm                          [ausgeschaltet]
  -mssse3                               [ausgeschaltet]
  -mstack-arg-probe                     [ausgeschaltet]
  -mstackrealign                        [eingeschaltet]
  -mstringop-strategy=                  [Standard]

I find it confusingly here, or at least very imprecise, that all sse instructions are shown as disabled, although the CPU should have it enabled up to the SSSE3 instruction set.

Instead the output of gcc -march=native -E -v - </dev/null 2>&1 | grep cc1 shows:
Code:

/usr/libexec/gcc/x86_64-pc-linux-gnu/4.7.2/cc1 -E -quiet -v - -march=core2 -mcx16 -msahf -mno-movbe -mno-aes -mno-pclmul -mno-popcnt -mno-abm -mno-lwp -mno-fma -mno-fma4 -mno-xop -mno-bmi -mno-bmi2 -mno-tbm -mno-avx -mno-avx2 -mno-sse4.2 -mno-sse4.1 -mno-lzcnt -mno-rdrnd -mno-f16c -mno-fsgsbase --param l1-cache-size=32 --param l1-cache-line-size=64 --param l2-cache-size=4096 -mtune=core2

Your explanation from you post before, for this kind of output is clear to me now.
Also the gcc doc shows the properties for the CPU family as:
Quote:
‘core2’
Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support.


The totally different behaviour of your output, what you have shown for gcc -Q --help=target -march=native
doesn't correlate with mine and with the logic of the description.

Code:
  -msse                             [enabled]
  -msse2                            [enabled]
  -msse2avx                         [disabled]
  -msse3                            [enabled]

Following this, yours should not be shown, cause it's imply in your family as shown here:
corei7’
Intel Core i7 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 instruction set support. [/quote]

Or, mine must be shown as enabled too, for SSE, SSE2, SSE3 and SSSE3, shouldn't it?
So how to trust or explain this kind of different behaviour of the output of gcc -Q --help=target -march=native?

At least the other one of gcc -march=native -E -v - </dev/null 2>&1 | grep cc1 seems to be correct on my system.

As my conclusion of this thread, I would like to edit my CFLAGS in the make.conf fo the future in a way, where I copy and paste the output of

Code:
CFLAGS="-march=core2 -mcx16 -msahf -mno-movbe -mno-aes -mno-pclmul -mno-popcnt -mno-abm -mno-lwp -mno-fma -mno-fma4 -mno-xop -mno-bmi -mno-bmi2 -mno-tbm -mno-avx -mno-avx2 -mno-sse4.2 -mno-sse4.1 -mno-lzcnt -mno-rdrnd -mno-f16c -mno-fsgsbase --param l1-cache-size=32 --param l1-cache-line-size=64 --param l2-cache-size=4096 -mtune=core2 -O2 -pipe -fomit-frame-pointer"

to get the same properties as using march=native, for distcc or chroot compiling reasons.

Would you agree this strategy for that conditions?

I know I could get Illegal instructions when doing so, for 32Bit chroot compiling under the thread conditions, but now I know how to prevent them.

Best regards, Andy.
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krinn
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PostPosted: Wed Apr 03, 2013 8:01 pm    Post subject: Reply with quote

Yes i have check with my core2 and it always keep mmx, sse and the like disable, must be some kind of bug with core2.
But if you force it enable, it should confirm it, just try checking sse status with
Code:
gcc -Q --help=target -march=core2 -msse

(eheh now redo with all that need to be enable)

Because of that i didn't need to modify gcc for the corei7, but i have add all disabled features to my core2 to reenable them (to make sure it handle them). Even i think it should be safe to kept default.

Code:
-march=core2 -mcx16 -msahf -mno-movbe -mno-aes -mno-pclmul -mno-popcnt -mno-abm -mno-lwp -mno-fma -mno-fma4 -mno-xop -mno-bmi -mno-bmi2 -mno-tbm -mno-avx -mno-avx2 -mno-sse4.2 -mno-sse4.1 -mno-lzcnt -mno-rdrnd -mno-f16c -mno-fsgsbase --param l1-cache-size=32 --param l1-cache-line-size=64 --param l2-cache-size=4096 -mtune=core2 -mmmx -msse -msse2 -msse3 -mssse3 -mfpmath=sse   


For your illegal instruction, i would have copy any -mno-param from the core2 into the atom cflags, making sure any disable function for the core2 will also be force disable for the atom.
As you also use distcc, choice is getting harder: less optimize and chroot, more optimize and distcc.
I would have use distcc solution, as even it build them slower than the chroot, it wouldn't lower perf of the atom because of less optimize for that cpu family.
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PostPosted: Wed Apr 03, 2013 9:01 pm    Post subject: Reply with quote

This "gcc -Q --help=target -march=" Output is confusing
see http://gcc.gnu.org/bugzilla/show_bug.cgi?id=39851
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PostPosted: Sat Apr 06, 2013 12:14 pm    Post subject: Reply with quote

What a bad awaking for me, krinn.

Now, after 6 (in terms six!) years of using and optimizing gentoo, I had to find out that (at least) two of my most performant machines, doesn't use any of the built in mmx and sse instruction sets. What a f... äh pity!
The older ones I will check later.

Not only when using gcc automatic detection (march=native) I'd never used, then I would know, automatisms could fail sometimes and that's exactly why I'm using gentoo and did the most things manually.

Now, also when following the Safe-Cflags documentation, which was recommended by the handbook, the fault was still the same. I guess there should be given a hint in future releases, how to check if the settings are in used or not, as it was in my case.

I found out that neither on my quad core, nor on my atom, the mmx and sse instruction sets are active, if I doesn't mentioned it explicit for my CFLAGS.
I tried out gcc-4.6.3 and 4.7.2, both with the same behaviour.
All of the documentation I read before, told me that it's included into the -march=core2 -mtune=core2 or into the -march=atom -mfpmath=sse ssettings I used before and there is no need to add it explicitly, or did I misinterpret it.

Actually I'm recompiling my atom's world (>1200 packages), the quad core is already done (>1600 packages!) activating all of it supported instruction sets, knowing that I lost the chroot compiling for the atom in this way.
I'm more interested in the additional performance. Now I need a good benchmark suite, to compare the before and after adjusted systems, which are apart from that, still the same.


When I had opened this thread, I'd never thought about this kind of findings, it would have brought to me.
So at the end, I'm happy to opened this thread.

Many thanks and best regards,

Andy.
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