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rdivincenzo
Tux's lil' helper
Tux's lil' helper


Joined: 01 Apr 2006
Posts: 79

PostPosted: Tue Sep 20, 2011 7:33 am    Post subject: Installation on Fujitsu Siemens PRIMEPOWER450 4x SPARC64 V Reply with quote

Hi, I'm using gentoo for Sparc ,
but after command "boot cdrom" from obp I get:

Code:


.Sep 19 08:56:49 MEST 2011 XSCF:I::[02030100] Start reset sequence
Sep 19 08:56:49 MEST 2011 XSCF:I::[02030200] Reset released...

Sep 19 06:56:52 GMT 2011 PowerOn SelfTest start
POST:Testing Flash/SRAM
POST:Testing SC
POST:Testing XSCF
POST:Banner
POST:FATAL check
POST:Testing Timer1
POST:Testing Tick
POST:Testing MMU
POST:Testing CPU Type
POST:Testing DTAG
POST:Memory Probe
POST:Testing Memory
POST:Testing Softint
POST:Testing U2P
POST:Testing Slave Device
POST:Testing Master Device
POST:System Configure
POST:OBP Start
screen:r1024x768x75 not found.
keyboard not found.

Fujitsu Siemens PRIMEPOWER450 4x SPARC64 V, No Keyboard
OpenBoot 3.14.1-1, 16384 MB memory installed
Ethernet address 0:e0:0:c4:c1:9a, Host ID: 80f3c19a.
XSCF Version: 4.2.1



{0} ok
{0} ok
{0} ok boot cdrom
Boot device: /pci@83,4000/ide@d/cdrom@0,0:f  File and args:
SILO Version 1.4.14
\

----------------------------------------------------
Welcome to the Gentoo/Linux SPARC64 weekly InstallCD
----------------------------------------------------

boot: gentoo
Allocated 64 Megs of memory at 0x40000000 for kernel
Loaded kernel version 2.6.39
Loading initial ramdisk (2334417 bytes at 0x5FF800000 phys, 0x40C00000 virt)...
-
PROMLIB: Sun IEEE Boot Prom 'OBP 3.14.1 2005/02/09 08:39'
PROMLIB: Root node compatible: sun4us
Linux version 2.6.39-gentoo-r3 (root@bender) (gcc version 4.4.4 (Gentoo 4.4.4 p1.0) ) #1 SMP Mon Sep 12 21:02:54 UTC 2011
bootconsole [earlyprom0] enabled
ARCH: SUN4U
Ethernet address: 00:e0:00:c4:c1:9a
Kernel: Using 2 locked TLB entries for main kernel image.
Remapping the kernel... done.
RED State Exception ( CPU#0 )
Resetting ...

.Sep 19 09:12:30 MEST 2011 XSCF:I::[02030100] Start reset sequence
Sep 19 09:12:31 MEST 2011 XSCF:I::[02030200] Reset released...


I have test sistem with openBSD, and installation go fine.
I try to enable debug information with setenv mfg-mode on and setenv diag-switch? true

Code:

Code:

{0} setenv mfg-mode on
mfg-mode =            on
{0} setenv diag-switch? true
diag-switch? =        true

{0} ok reset-all


Il risultato è il seguente:

Code:

Resetting ...

.Sep 19 10:26:14 MEST 2011 XSCF:I::[02030100] Start reset sequence
Sep 19 10:26:14 MEST 2011 XSCF:I::[02030200] Reset released...

Sep 19 08:26:17 GMT 2011 PowerOn SelfTest start
0>Flash/SRAM Test
2>slave_wait...
1>slave_wait...
3>slave_wait...
0>      Flash Memory check sum Test
0>      FROM#0 checksum = 10fe51fe
0>      FROM#1 checksum = 11047ed3
0>      SRAM Data Line Test
0>      SRAM Addr Line Test
0>      SRAM Data Test
0>      SRAM Init Test
1>slave_wait...
2>slave_wait...
3>slave_wait...
0>SC Test
0>      SC init
2>slave_wait...
0>XSCF Test
3>slave_wait...
1>slave_wait...
0>      XSCF Test
0>      CPU Status Test
0>Banner
3>Banner
1>Banner
3>      PowerOn SelfTest 14.1.1, created 02/09/2005 08:45:00
1>      PowerOn SelfTest 14.1.1, created 02/09/2005 08:45:00
3>      ID=4090fc26.10fa00a2(HG1V26G 0902)
1>      ID=6090fc26.98fa0462(HY1V6MG 0906)
2>Banner
3>      SPARC64V(mask=08)
1>      SPARC64V(mask=08)
3>      CPU_UPA_CONFIG=3e801001.7bc6803b
1>      CPU_UPA_CONFIG=3e801001.7bc2803b
0>      PowerOn SelfTest 14.1.1, created 02/09/2005 08:45:00
2>      PowerOn SelfTest 14.1.1, created 02/09/2005 08:45:00
0>      ID=a020fde4.0853421e(U4BA42U 0405)
2>      ID=1060fc2b.0a810d22(HB21KDG 0608)
1>      WB_S=8, WRI_S=8, INT_S=8
3>      WB_S=8, WRI_S=8, INT_S=8
2>      SPARC64V(mask=08)
3>      MCAP=0, CLK_MODE=5:1
1>      MCAP=0, CLK_MODE=5:1
0>      SPARC64V(mask=08)
1>      SCIQ0=8, SCIQ1=8
2>      CPU_UPA_CONFIG=3e801001.7bc4803b
3>      SCIQ0=8, SCIQ1=8
2>      WB_S=8, WRI_S=8, INT_S=8
0>      CPU_UPA_CONFIG=3e801001.7bc0803b
2>      MCAP=0, CLK_MODE=5:1
0>      WB_S=8, WRI_S=8, INT_S=8
2>      SCIQ0=8, SCIQ1=8
0>      MCAP=0, CLK_MODE=5:1
0>      SCIQ0=8, SCIQ1=8
1>      diag-switch?=true, diag-level=min
        configuration-policy=component
3>      diag-switch?=true, diag-level=min
        configuration-policy=component
2>      diag-switch?=true, diag-level=min
        configuration-policy=component
0>      diag-switch?=true, diag-level=min
        configuration-policy=component
0>FATAL check
2>FATAL check
3>FATAL check
2>      FATAL reset check1
1>FATAL check
2>      FATAL reset check2
0>      FATAL reset check1
1>      FATAL reset check1
3>      FATAL reset check1
1>      FATAL reset check2
3>      FATAL reset check2
0>      FATAL reset check2
0>Timer1 Test
1>Timer1 Test
3>Timer1 Test
2>Timer1 Test
3>      Timer1 Increment Test
1>      Timer1 Increment Test
2>      Timer1 Increment Test
1>      Probing Timer at 100.00001c10
0>      Timer1 Increment Test
3>      Probing Timer at 100.00001c10
1>      Probing Timer at 106.00001c10
0>      Probing Timer at 100.00001c10
2>      Probing Timer at 100.00001c10
3>      Probing Timer at 106.00001c10
2>      Probing Timer at 106.00001c10
0>      Probing Timer at 106.00001c10
0>Tick Test
1>Tick Test
2>Tick Test
1>      Tick Increment Test
2>      Tick Increment Test
3>Tick Test
3>      Tick Increment Test
0>      Tick Increment Test
0>MMU Test
3>MMU Test
1>MMU Test
2>MMU Test
1>      MMU Registers Test
3>      MMU Registers Test
2>      MMU Registers Test
0>      MMU Registers Test
1>      MMU TLBs Test
1>      fITLB Tests
2>      MMU TLBs Test
3>      MMU TLBs Test
2>      fITLB Tests
3>      fITLB Tests
1>      fDTLB Tests
1>      sITLB Tests
3>      fDTLB Tests
2>      fDTLB Tests
3>      sITLB Tests
1>      sDTLB Tests
3>      sDTLB Tests
2>      sITLB Tests
1>      MMU Init
2>      sDTLB Tests
3>      MMU Init
0>      MMU TLBs Test
2>      MMU Init
0>      fITLB Tests
0>      fDTLB Tests
0>      sITLB Tests
0>      sDTLB Tests
0>      MMU Init
0>CPU Type Test
3>CPU Type Test
2>CPU Type Test
1>CPU Type Test
3>      CPU type check
1>      CPU type check
0>      CPU type check
2>      CPU type check
1>slave_wait...
2>slave_wait...
0>DTAG Test
3>slave_wait...
0>      DTAG  Test
0>      DTAG Init
1>slave_wait...
3>slave_wait...
2>slave_wait...
0>Memory Probe
0>      MC Init
0>      Memory Probe
0>       slot0 : 1024mb + 1024mb       slot1 : 1024mb + 1024mb
         slot2 :    0mb +    0mb       slot3 :    0mb +    0mb
         slot4 : 1024mb + 1024mb       slot5 : 1024mb + 1024mb
         slot6 :    0mb +    0mb       slot7 :    0mb +    0mb
         slot8 : 1024mb + 1024mb       slot9 : 1024mb + 1024mb
        slot10 :    0mb +    0mb      slot11 :    0mb +    0mb
0>      slot12 : 1024mb + 1024mb      slot13 : 1024mb + 1024mb
0>      slot14 :    0mb +    0mb      slot15 :    0mb +    0mb
0>      Memory Configuration
1>Memory Test
2>Memory Test
1>      Memory Address Line Test
3>Memory Test
2>      Memory Address Line Test
1>      Simple Memory Test
3>      Memory Address Line Test
2>      Simple Memory Test
0>Memory Test
3>      Simple Memory Test
0>      Memory Address Line Test
0>      Simple Memory Test
0>      Verifying Addr=00000000.00000000, Size=00000002.00000000
1>      Verifying Addr=00000004.00000000, Size=00000002.00000000
0>      Syncing ...0>   done ...
0>      next_state=05
2>      Memory Init
3>      Memory Init
1>      Memory Init
0>      Memory Init
0>      Initializing: address=00000000.00000000, size=00000002.00000000
1>      Initializing: address=00000004.00000000, size=00000002.00000000
1>slave_wait...
2>slave_wait...
3>slave_wait...
0>Softint Test
1>Softint Test
3>Softint Test
2>Softint Test
3>      Softint Registers and Interrupt Test
1>      Softint Registers and Interrupt Test
2>      Softint Registers and Interrupt Test
3>      Tick and Tick Compare Regs. Test
2>      Tick and Tick Compare Regs. Test
0>      Softint Registers and Interrupt Test
1>      Tick and Tick Compare Regs. Test
3>      Stick and Stick Compare Regs. Test
0>      Tick and Tick Compare Regs. Test
1>      Stick and Stick Compare Regs. Test
2>      Stick and Stick Compare Regs. Test
0>      Stick and Stick Compare Regs. Test
0>U2P Test
3>slave_wait...
1>slave_wait...
2>slave_wait...
0>      U2P Probe
0>      Probing U2P#0(0x80) at 100.00000000
0>      Probing U2P#3(0x83) at 106.00000000
0>      U2P Registers Test
0>      IO0_Status= 01000000(MC0Q=2), UPA_Config=00000002
0>      Testing U2P port_id=80
0>      IO3_Status= 01000000(MC0Q=2), UPA_Config=00000002
0>      Testing U2P port_id=83
0>      U2P Interrupts Test
0>      Testing U2P#3(portid=83,inr=20ee)
0>      Testing U2P#3(portid=83,inr=20ef)
0>      Testing U2P#3(portid=83,inr=20f0)
0>      Testing U2P#3(portid=83,inr=20f1)
0>      Testing U2P(Timer)#3(portid=83,inr=20ec)
0>      Testing U2P(Timer)#3(portid=83,inr=20ed)
0>      Testing SCSI#0(portid=83,inr=20e0)
0>      Testing LAN#0(portid=83,inr=20e1)
0>      Testing ATAPI#0(portid=83,inr=20e4)
0>      Testing SCSI#1(portid=83,inr=20e6)
0>      Testing USBC(portid=83,inr=20e9)
0>      Testing LAN#1(portid=83,inr=20ea)
0>      Testing U2P#0(portid=80,inr=202e)
0>      Testing U2P#0(portid=80,inr=202f)
0>      Testing U2P#0(portid=80,inr=2030)
0>      Testing U2P#0(portid=80,inr=2031)
0>      Testing U2P(Timer)#0(portid=80,inr=202c)
0>      Testing U2P(Timer)#0(portid=80,inr=202d)
0>      Testing PCI#00(portid=80,inr=2000)
0>      Testing PCI#00(portid=80,inr=2001)
0>      Testing PCI#00(portid=80,inr=2002)
0>      Testing PCI#00(portid=80,inr=2003)
0>      Testing PCI#01(portid=80,inr=2004)
0>      Testing PCI#01(portid=80,inr=2005)
0>      Testing PCI#01(portid=80,inr=2006)
0>      Testing PCI#01(portid=80,inr=2007)
0>      Testing PCI#02(portid=80,inr=2010)
0>      Testing PCI#02(portid=80,inr=2011)
0>      Testing PCI#02(portid=80,inr=2012)
0>      Testing PCI#02(portid=80,inr=2013)
0>      Testing PCI#03(portid=80,inr=2014)
0>      Testing PCI#03(portid=80,inr=2015)
0>      Testing PCI#03(portid=80,inr=2016)
0>      Testing PCI#03(portid=80,inr=2017)
0>      Testing PCI#04(portid=80,inr=2018)
0>      Testing PCI#04(portid=80,inr=2019)
0>      Testing PCI#04(portid=80,inr=201a)
0>      Testing PCI#04(portid=80,inr=201b)
0>      Testing PCI#05(portid=83,inr=20d0)
0>      Testing PCI#05(portid=83,inr=20d1)
0>      Testing PCI#05(portid=83,inr=20d2)
0>      Testing PCI#05(portid=83,inr=20d3)
0>      U2P Timers/Counters Test
0>      Testing U2P(Timer)#0(port_id=80)
0>      Testing U2P(Timer)#3(port_id=83)
0>      U2P Functional Test
0>      Testing U2P port_id=80
0>      IOMMU Tag Comparator Test
0>      Streaming Buffer Test
0>      DMA Merge Buffer Test
0>      Testing U2P port_id=83
0>      IOMMU Tag Comparator Test
0>      Streaming Buffer Test
0>      DMA Merge Buffer Test
0>      U2P Init
0>      Initializing U2P#0(port_id=80)
0>      IO0_Status= 01000000(MC0Q=2), UPA_Config=00000002
0>      Initializing U2P#3(port_id=83)
0>      IO3_Status= 01000000(MC0Q=2), UPA_Config=00000002
0>      U2P PCI slot Test
0>      Probing PCI#00 at 100.01800800 :
                func#0 : Fibre Channel
0>      Probing PCI#01 at 100.01801000 :
                func#0 : Fibre Channel
0>      Probing PCI#02 at 100.01001800 :
                func#0 : Ethernet
0>      Probing PCI#03 at 100.01002000 :
                func#0 : Ethernet
0>      Probing PCI#04 at 100.01002800 :
0>      Probing PCI#05 at 106.01001800 :
0>Slave Device Test
3>slave_wait...
1>slave_wait...
2>slave_wait...
0>      TOD Test
0>      TTY Test
0>      HPC3130 Test
0>      SLOT LED
0>Master Device Test
3>slave_wait...
2>slave_wait...
1>slave_wait...
0>      Ethernet Registers Test
0>      Ethernet Internal Loopback Test
0>      Ethernet PHY Loopback(10Mbps) Test
0>      Ethernet PHY Loopback(100Mbps) Test
0>      Ultra320 Registers Test
0>      GIGA-Ether Registers Test
0>      IDE Registers Test
0>      106.02010407:busy wait...0>done
0>      USB Test
0>      Port #00 Test
0>      Port #01 Test
0>System Configure
2>slave_wait...
3>slave_wait...
1>slave_wait...
0>                   UPA module(Processor)
0>      -----+--------+-------------+-------+-----+------------
0>       mid | Status |    Type     | Cache | Ver.| freq.
0>      -----+--------+-------------+-------+-----+------------
0>        0  |   OK   |  SPARC64V   |  1mb  | 08  | 1100mhz
0>        1  |   OK   |  SPARC64V   |  1mb  | 08  | 1100mhz
0>        2  |   OK   |  SPARC64V   |  1mb  | 08  | 1100mhz
0>        3  |   OK   |  SPARC64V   |  1mb  | 08  | 1100mhz
0>      -----+--------+-------------+-------+-----+------------
0>                      I/O
0>      ----------------------------------------------
0>      SCSI#0  OK(87)  U2P#3B,dev#02,func#00
0>      SCSI#1  OK(87)  U2P#3B,dev#02,func#01
0>      LAN#0   OK(87)  U2P#3B,dev#01,func#01
0>      LAN#1   OK(87)  U2P#3A,dev#01,func#00
0>      ATAPI#0 OK(87)  U2P#3B,dev#0d,func#00
0>      USBC    OK(87)  U2P#3B,dev#0a,func#00
0>      PCI#00  OK(87)  U2P#0A,dev#01,func#00
0>      PCI#01  OK(87)  U2P#0A,dev#02,func#00
0>      PCI#02  OK(87)  U2P#0B,dev#03,func#00
0>      PCI#03  OK(87)  U2P#0B,dev#04,func#00
0>      PCI#04  OK(87)  U2P#0B,dev#05,func#00
0>      PCI#05  OK(87)  U2P#3B,dev#03,func#00
0>      ----------------------------------------------
0>OBP Start
2>OBP Start
2>      Enter OBP
1>OBP Start
3>OBP Start
1>      Enter OBP
3>      Enter OBP
0>      Enter OBP
0>      Sending CPU#1 to OBP
0>      Sending CPU#2 to OBP
0>      Sending CPU#3 to OBP
0>      Entering OBP
Entering OBP:.
Probing memory ... Done
MEM BASE = 0000.0005.fc00.0000
MEM SIZE = 0000.0000.0400.0000
Clearing memory   Done
MMUs On
Copying ROM to RAM...Done

ROM PC = 0000.01ff.f000.99dc
RAM PC = 0000.0000.0000.9a10
Copying forth...Done
Decompressing into Memory...Done
Size = 0000.0000.000b.dc10  (760KB)

ttya initialized
Probing UPA Slot at 83,0     pci pci counter-timer
Probing UPA Slot at 80,0     pci pci counter-timer
counter is /counter-timer@83,1c00
ebus
Probing /pci@83,4000/ebus@1  FJSV,scfc
Probing memory : 16384 MB
mc dimm dimm dimm dimm dimm dimm dimm dimm
Probing /pci@83,4000/ebus@1  FJSV,flashprom eeprom FJSV,panel
Probing UPA Slot at 0,0     FJSV,SPARC64-V
Probing UPA Slot at 1,0     FJSV,SPARC64-V
Probing UPA Slot at 2,0     FJSV,SPARC64-V
Probing UPA Slot at 3,0     FJSV,SPARC64-V
Loading Support Packages: kbd-translator
Probing /pci@83,4000 at Device 7  isa su su
Probing /pci@83,4000 at Device 1  network
Probing /pci@83,4000 at Device 2  FJSV,ulsa disk tape FJSV,ulsa disk tape
Probing /pci@83,4000 at Device d  ide disk cdrom
Probing /pci@83,4000 at Device a  usb
Probing /pci@83,4000 at Device 3  Nothing there
Probing /pci@83,2000 at Device 1  FJSV,pwga
Probing /pci@80,4000 at Device 5  Nothing there
Probing /pci@80,4000 at Device 4  FJSV,pgtb
Probing /pci@80,4000 at Device 3  FJSV,pgtb
Probing /pci@80,2000 at Device 2  fibre-channel
Probing /pci@80,2000 at Device 1  fibre-channel
screen not found.
keyboard not found.
Keyboard not present.  Using ttya for input and output.
Probing UPA Slot at 83,0     pci pci counter-timer
Probing UPA Slot at 80,0     pci pci counter-timer
counter is /counter-timer@83,1c00
ebus
Probing /pci@83,4000/ebus@1  FJSV,scfc
Probing memory : 16384 MB
mc dimm dimm dimm dimm dimm dimm dimm dimm
Probing /pci@83,4000/ebus@1  FJSV,flashprom eeprom FJSV,panel
Probing UPA Slot at 0,0     FJSV,SPARC64-V
Probing UPA Slot at 1,0     FJSV,SPARC64-V
Probing UPA Slot at 2,0     FJSV,SPARC64-V
Probing UPA Slot at 3,0     FJSV,SPARC64-V
Loading Support Packages: kbd-translator
Probing /pci@83,4000 at Device 7  isa su su
Probing /pci@83,4000 at Device 1  network
Probing /pci@83,4000 at Device 2  FJSV,ulsa disk tape FJSV,ulsa disk tape
Probing /pci@83,4000 at Device d  ide disk cdrom
Probing /pci@83,4000 at Device a  usb
Probing /pci@83,4000 at Device 3  Nothing there
Probing /pci@83,2000 at Device 1  FJSV,pwga
Probing /pci@80,4000 at Device 5  Nothing there
Probing /pci@80,4000 at Device 4  FJSV,pgtb
Probing /pci@80,4000 at Device 3  FJSV,pgtb
Probing /pci@80,2000 at Device 2  fibre-channel
Probing /pci@80,2000 at Device 1  fibre-channel

Fujitsu Siemens PRIMEPOWER450 4x SPARC64 V, No Keyboard
OpenBoot 3.14.1-1, 16384 MB memory installed
Ethernet address 0:e0:0:c4:c1:9a, Host ID: 80f3c19a.
XSCF Version: 4.2.1



board
{0} ok


Thanks for all, sorry for my bad english.
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