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taviso
Retired Dev
Joined: 15 Apr 2003
Posts: 261
Location: United Kingdom
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 Posted: Tue Jul 15, 2003 3:52 pm Post subject: x86 Feature Flags |
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I often see questions on irc like "what does xxx flag mean in /proc/cpuinfo?", or "does xxx flag mean I have this feature?", so ive decided to put together this quick reference.
Search Bait: | Code: | | cpuinfo feature flags registers |
- fpu
Floating Point Unit, the processor contains an FPU that supports the Intel387 floating-point instruction set.
- vme
Virtual Mode Extension, the processor supports extensions to virtual-8086 mode.
- de
Debugging Extension, the processor supports I/O breakpoints, including debug extensions and DR4/DR5 register trapping.
- pse
Page Size Extension, the processor supports 4-Mbyte pages.
- tsc
Time Stamp Counter, The RDTSC instruction is supported including access/privilege control.
- msr
Model Specific Registers, registers implemented with the RDMSR, WRMSR instructions
- pae
Physical Address Extension, Physical addresses greater than 32 bits are supported.
- mce
Machine Check Exception, Exception 18, and the CR4.MCE enable bit are supported
- cx8
The compare and exchange 8 bytes instruction is supported.
- apic
On-chip APIC Hardware Supported, the processor contains a software-accessible Local APIC.
- sep
Fast System Call, the processor supports the Fast System Call instructions, SYSENTER and SYSEXIT.
- mtrr
Memory Type Range Registers, the Processor supports the Memory Type Range Registers, specifically the MTRR_CAP register.
- pge
Page Global Enable, the global bit in the page directory entries (PDEs) and page table entries (PTEs) is supported, indicating TLB entries that are common to different processes and need not be flushed.
- mca
The Machine Check Architecture is supported, specifically the MCG_CAP register.
- cmov
The processor supports CMOVcc, and if the FPU feature flag (bit 0) is also set, supports the FCMOVCC and FCOMI instructions.
- pat
Indicates whether the processor supports the Page Attribute Table. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory on 4K granularity through a linear address.
- pse-36
36-bit Page Size Extension, indicates whether the processor supports 4-Mbyte pages that are capable of addressing physical memory beyond 4GB.
- pn
Processor serial number is present and enabled.
- clflush
Indicates that the processor supports the CLFLUSH instruction.
- dts
Debug Store Indicates that the processor has the ability to write a history of the branch to and from addresses into a memory buffer.
- acpi
The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control.
- mmx
The processor supports the MMX technology instruction set extensions to Intel Architecture.
- fxsr
Indicates whether the processor supports the FXSAVE and FXRSTOR instructions for fast save and restore of the floating point context.
- sse
The processor supports the Streaming SIMD Extensions to the Intel Architecture.
- sse2
Indicates the processor supports the Streaming SIMD Extensions - 2 Instructions.
- ss
Self Snoop, the processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus.
- ht
Hyper-Threading Technology, this processor has the capability to operate as multiple logical processors within the same physical package. This field does not indicate that Hyper-Threading Technology has been enabled for this specific processor, only that support is present.
- tm
The processor implements the Thermal Monitor automatic thermal control circuit (TCC).
And for AMD users:
- syscall
The SYSCALL and SYSRET instructions and associated extensions are supported.
- mp
Indicates the processor contains the Athlon MP Model6 extended instructions
- mmxext
Indicates the processor supports MMX instruction extensions.
- 3dnow
Indicates the processor contains 3dNow! instructions
- 3dnowext
Indicates the processor contains 3DNow! instruction extensions
References:
arch/i386/kernel/setup.c
Intel Developer Documentation: Pentium4 Xeon CPUID
AMD developer documentation: BIOS design guide.
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Gentoo on Alpha, is your penguin 64bit?
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Last edited by taviso on Sat Sep 20, 2003 5:27 pm; edited 1 time in total |
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EugeneTSWong
n00b
Joined: 18 Sep 2003
Posts: 45
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| Posted: Sat Sep 20, 2003 4:24 am Post subject: |
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| Thanks. I'm surprised that nobody said anything in this thread. |
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blue.sca
l33t
Joined: 28 Aug 2003
Posts: 680
Location: Mainz, Germany
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| Posted: Sat Sep 20, 2003 12:35 pm Post subject: |
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thats a nice overview, sad i have so little flags with my athlon  |
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verbatim
Apprentice
Joined: 13 Mar 2003
Posts: 223
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| Posted: Sat Sep 20, 2003 3:48 pm Post subject: |
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Thanks for the info. 
I think one clarification needs to be made though... "mmxext" doesn't indicate the MMX instruction set, it's the same deal as "3dnow" and "3dnowext", with "mmx"=standard MMX, and then "mmxext" for special extensions. |
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taviso
Retired Dev
Joined: 15 Apr 2003
Posts: 261
Location: United Kingdom
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| Posted: Sat Sep 20, 2003 5:30 pm Post subject: |
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| EugeneTSWong wrote: | | Thanks. I'm surprised that nobody said anything in this thread. |
I had almost forgotten i'd written this, im glad you found it useful!
| verbatim wrote: | | I think one clarification needs to be made though... "mmxext" doesn't indicate the MMX instruction set, it's the same deal as "3dnow" and "3dnowext", with "mmx"=standard MMX, and then "mmxext" for special extensions. |
well spotted, i'll update it
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Gentoo on Alpha, is your penguin 64bit?
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macslashback
n00b
Joined: 08 Sep 2003
Posts: 1
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| Posted: Sun Nov 09, 2003 12:52 pm Post subject: |
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| just what i was lookin for, thanks dude. |
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mr.twemlow
Tux's lil' helper
Joined: 12 Nov 2003
Posts: 90
Location: Illinois
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| Posted: Wed Nov 12, 2003 1:18 am Post subject: questions |
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| does that mean that any athlon supports sse, mmx, mmxext, 3dnow, and 3dnowext? i've got a 2000+ and i'm trying to figure out what flags i can use on it. |
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beowulf
Apprentice
Joined: 07 Apr 2003
Posts: 225
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| Posted: Wed Nov 12, 2003 7:48 am Post subject: |
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Thanks for the info! Wondered about a few of them....
To figure out what cpu flags your cpu supports, you could try this command:
| Code: | | $ cat /proc/cpuinfo | grep flags |
It should return the supported flags....
[edit: fixed a typo /]
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mr.twemlow
Tux's lil' helper
Joined: 12 Nov 2003
Posts: 90
Location: Illinois
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Genone
Retired Dev
Joined: 14 Mar 2003
Posts: 9530
Location: beyond the rim
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| Posted: Sun Nov 16, 2003 5:28 am Post subject: Re: questions |
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| mr.twemlow wrote: | | does that mean that any athlon supports sse, mmx, mmxext, 3dnow, and 3dnowext? i've got a 2000+ and i'm trying to figure out what flags i can use on it. |
Only Athlon-XPs have sse, but your 2000+ should be ok with sse. |
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carrotcake
n00b
Joined: 10 Apr 2004
Posts: 1
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| Posted: Sat Apr 10, 2004 8:01 pm Post subject: |
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| awesome |
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Anior
Guru
Joined: 17 Apr 2003
Posts: 317
Location: European Union (Stockholm / Sweden)
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| Posted: Wed May 18, 2005 10:31 am Post subject: |
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Some more flags:
AMD:
nx
Support the No eXecute bit. Making it possible to specify a memory area that only contains data.
lm
Support for Long Mode. AMDs 64 bit extention.
Transmeta:
recovery
Recovery CMS is active (after a bad flash).
longrun
Supports LongRun (shows up even if not activated)
lrti
No idea, please tell me if you know.
Other, add explanations if you're bored:
cxmmx
k6_mtrr
cyrix_arr
centaur_mcr |
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obrut<-
Apprentice
Joined: 01 Apr 2005
Posts: 183
Location: near hamburg, germany
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| Posted: Tue Jul 25, 2006 5:11 pm Post subject: |
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intel and amd:
pni: prescott new instructions aka sse3 |
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roderick
l33t
Joined: 11 Jul 2005
Posts: 908
Location: St. John's, NL CANADA
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| Posted: Wed Jul 26, 2006 3:33 am Post subject: |
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This is great. Bookmarked
Here's my flags. Some are not in your list. WOuld be great to know what the others are? (Like nx).
Thanks.
| Code: |
fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss tm pbe nx
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pactoo
Guru
Joined: 18 Jul 2004
Posts: 553
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| Posted: Wed Jul 26, 2006 6:55 am Post subject: |
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| vmx flag is also missing, indicating vanderpool (also pacifica?) technology |
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Anior
Guru
Joined: 17 Apr 2003
Posts: 317
Location: European Union (Stockholm / Sweden)
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| Posted: Fri Jul 28, 2006 9:16 pm Post subject: |
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| roderick wrote: | | Here's my flags. Some are not in your list. WOuld be great to know what the others are? (Like nx). |
Taviso went missing in action last October so he's rather unlikely to read this. There are some more flags if you read the complete thread though:
| Anior wrote: | Some more flags:
AMD:
nx
Support the No eXecute bit. Making it possible to specify a memory area that only contains data.
... |
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zietbukuel
l33t
Joined: 30 Dec 2005
Posts: 607
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| Posted: Sun Jul 30, 2006 2:50 am Post subject: |
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There are my flags:
| Code: | | fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt lm 3dnowext 3dnow pni lahf_lm |
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