Since some time I'm toying around with Raspberry Pi's Pico board. The SoC has two ARM Cortex-M0+ cores and the "Getting started" document (https://datasheets.raspberrypi.org/pico ... h-pico.pdf) is pretty Ubuntu focused and thus assumes the binary toolchain. I thought I can do better with Gentoo and crossdev and emerged the toolchain for target arm-none-eabi. Generally, it's all working fine, until recently a specific program made the Pico board crash. I debugged it to being the "strcmp" function leading to an exception in the CPU. In the RaspberryPi Forums, I suspected the toolchain and this was also assumed to be the case by others: https://www.raspberrypi.org/forums/view ... 3#p1856673.
During the compilation of cross-arm-none-eabi/newlib, I can see that several variants are being built, tuned for several ARM instruction sets, including v5te and v7+fp. According to https://en.wikipedia.org/wiki/ARM_Corte ... ction_sets, the M0+ should have ARMv6-M architecture without FP.
I know very well how to tune my host compiler and Gentoo system for my specific host CPU but I'm a bit lost when it comes to tuning cross-arm-none-eabi/newlib for the Cortex-M0+ or actually making sure the toolchain doesn't emit instructions that are simply not supported by the chip, as it seems to be the case for strcmp.
I've had a look at /usr/arm-none-eabi/etc/portage/make.conf, /var/db/repos/localrepo-crossdev/cross-arm-none-eabi/newlib/newlib-4.1.0.ebuild and the "toolchain-funcs" eclass it uses but I could not find references to the v5te and v7+fp architectures being actually created.
