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Will GCC-6.1 be available anytime soon?
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asturm
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Joined: 05 Apr 2007
Posts: 5571
Location: Austria

PostPosted: Mon Sep 19, 2016 7:53 pm    Post subject: Reply with quote

ArneBab wrote:
That’s sad - the Gentoo wiki used to be the poster child of documentation.

Anyone can contribute, but someone needs to be first.
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janos666
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Joined: 15 Nov 2015
Posts: 16

PostPosted: Fri Oct 07, 2016 1:07 am    Post subject: Reply with quote

I recently had some trouble with GCC after changing some hardware in my home server, including a switch from AMD 5600K to Pentium G4400.

I usually had march=native in my make.conf and compiled the kernel the same way (gentoo-sources with the experimental flag to make this convenient). Obviously, I had to recompile everything for basic x86-64 before switching the hardware but the migration went fine up to that point. However, I had serious issues with switching back to march=native.

GCC 5.4 (~amd64) identified this CPU as "silvermont" which is quite similar (if not exactly the same?) in terms of instruction set support but it's not exactly the same architecture (this is a 14nm skylake desktop CPU, not a low-power SoC from the 22nm haswell era). Although, it seemed to get all the instruction sets right (the flags reported by /proc/cpuinfo and the debug output of gcc seemed to be in line, however, I didn't check all of them one-by-one, just looked for some obvious mistakes), thus using march=native resulted in incompatible code (I didn't expect a problem, so I completely messed up the whole system with emerge, I had to roll back to a snapshot).

So, I tried to run ahead of the problem and use 6.2-r1 (**) but it seemed to have even more problems. It correctly identified the CPU as "skylake" and it disabled most of the instruction sets which are not available at the entry level of this CPU lineup (the easiest example is probably the AVX family which is available only for Core i* and Xeon E* V5 but not for Pentium and Celeron variants), however it leaved some clearly incompatible sets enables (namely BMI1 and BMI2 - I have no idea why...?).

But strangely enough, after upgrading from gentoo-sources 4.7.6 to 4.8.0 (~amd64), GCC 6.2 started working fine. I wonder if this was:
1: a random bug (possibly related to the status of the GCC 6.2 ebuild)
2: the new kernel might produces a slightly different output on /proc/cpuinfo which might be easier for GCC 6.2 to understand...? (I never logged that output and didn't examine it closely before both GCC versions failed.)
3: while upgrading the kernel, I figured out how to use the early microcode update driver (I previously thought I get the microcode updated by the motherboard firmware but later realized that only updates CPU0 and leaves CPU1 at it's initial revision and there are 10+ skylake microcode updates since the platform's release, so rev0 probably has numerous issues which might weren't considered by the kernel since CPU0 was updated...).

Did anybody have similar experience?


There seems to remain a tiny issue still: both GCC versions detect the L1 cache size as 32KiB (l1-cache-size=32), even though it's 64KiB (according to both Intel's specs and dmidecode or lshw).
I am not sure if that's a bug but I can't create a GCC bug tracker account anyways.
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trippels
Tux's lil' helper
Tux's lil' helper


Joined: 24 Nov 2010
Posts: 137
Location: Berlin

PostPosted: Fri Oct 07, 2016 9:34 am    Post subject: Reply with quote

janos666 wrote:
I recently had some trouble with GCC after changing some hardware in my home server, including a switch from AMD 5600K to Pentium G4400.

I usually had march=native in my make.conf and compiled the kernel the same way (gentoo-sources with the experimental flag to make this convenient). Obviously, I had to recompile everything for basic x86-64 before switching the hardware but the migration went fine up to that point. However, I had serious issues with switching back to march=native.

GCC 5.4 (~amd64) identified this CPU as "silvermont" which is quite similar (if not exactly the same?) in terms of instruction set support but it's not exactly the same architecture (this is a 14nm skylake desktop CPU, not a low-power SoC from the 22nm haswell era). Although, it seemed to get all the instruction sets right (the flags reported by /proc/cpuinfo and the debug output of gcc seemed to be in line, however, I didn't check all of them one-by-one, just looked for some obvious mistakes), thus using march=native resulted in incompatible code (I didn't expect a problem, so I completely messed up the whole system with emerge, I had to roll back to a snapshot).

So, I tried to run ahead of the problem and use 6.2-r1 (**) but it seemed to have even more problems. It correctly identified the CPU as "skylake" and it disabled most of the instruction sets which are not available at the entry level of this CPU lineup (the easiest example is probably the AVX family which is available only for Core i* and Xeon E* V5 but not for Pentium and Celeron variants), however it leaved some clearly incompatible sets enables (namely BMI1 and BMI2 - I have no idea why...?).

But strangely enough, after upgrading from gentoo-sources 4.7.6 to 4.8.0 (~amd64), GCC 6.2 started working fine. I wonder if this was:
1: a random bug (possibly related to the status of the GCC 6.2 ebuild)
2: the new kernel might produces a slightly different output on /proc/cpuinfo which might be easier for GCC 6.2 to understand...? (I never logged that output and didn't examine it closely before both GCC versions failed.)
3: while upgrading the kernel, I figured out how to use the early microcode update driver (I previously thought I get the microcode updated by the motherboard firmware but later realized that only updates CPU0 and leaves CPU1 at it's initial revision and there are 10+ skylake microcode updates since the platform's release, so rev0 probably has numerous issues which might weren't considered by the kernel since CPU0 was updated...).

Did anybody have similar experience?


There seems to remain a tiny issue still: both GCC versions detect the L1 cache size as 32KiB (l1-cache-size=32), even though it's 64KiB (according to both Intel's specs and dmidecode or lshw).
I am not sure if that's a bug but I can't create a GCC bug tracker account anyways.


It is point 3 in your list. The initial firmware for you CPU was buggy and incorrectly reported BMI compatibility.
See: https://software.intel.com/en-us/forums/topic/584240 and
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/desktop-6th-gen-core-family-spec-update.pdf

And please open a gcc target bug for the L1 cache size issue.
(You will get an account if you send a plain text email request to: overseers@gcc.gnu.org)
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Nsane457
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Joined: 25 Nov 2004
Posts: 41

PostPosted: Thu Oct 26, 2017 4:47 am    Post subject: Reply with quote

So, I'm happy to announce that after having started this thread and actively working to fix the bugs, all GCC-6 related bugs are pretty much fixed. The few that remain either have a pull-request/patch pending or a reason as to why the package can't/shouldn't be fixed (most require version bumps). On to GCC-7...
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NeddySeagoon
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Joined: 05 Jul 2003
Posts: 39297
Location: 56N 3W

PostPosted: Thu Oct 26, 2017 9:42 am    Post subject: Reply with quote

Nsane457,

gcc-7 has been mostly working for me since just before it was unmasked. I was tempted for arm64 support.
My guess is that it won't be far behind gcc-6 and the /17.0/ profiles going stable.

gcc-7 probably deserves its own thread.
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