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clocksource: timekeeping watchdog on CPU4: Marking clocksource 'tsc' as unstable because the skew is too large:
[ 2.589702] clocksource: 'hpet' wd_nsec: 495453193 wd_now: 225c7ac wd_last: 1b988c8 mask: ffffffff
[ 2.589706] clocksource: 'tsc' cs_nsec: 503192819 cs_now: 347d06d8f cs_last: 308f28ac5 mask: ffffffffffffffff
[ 2.589710] clocksource: 'tsc' is current clocksource.
[ 2.589739] TSC found unstable after boot, most likely due to broken BIOS. Use 'tsc=unstable'.
[ 2.589934] clocksource: Checking clocksource tsc synchronization from CPU 0 to CPUs 1-2,4-5,7,9.$ cat /sys/devices/system/clocksource/clocksource0/current_clocksource
hpet
which is not what I want since tsc is using cpu registers instead of memory so it is much faster.
I have found this thread https://bugzilla.kernel.org/show_bug.cgi?id=216166, where the same error occurs on Ryzen processors and there it is suggested the problem is in bios. I have played around a bit though and have figured out the problem is in deep idle states, which is where tsc breaks. I am not sure why, but from what I understand, registers tsc is using are not designed to be the system clocksource, which is why tsc is not as reliable as hpet. I guess deep idle states are one of the things that break it. Since I have put in my /etc/default/grub
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GRUB_CMDLINE_LINUX_DEFAULT="processor.max_cstate=1 amd_pstate=passive"Code: Select all
$ cat /sys/devices/system/clocksource/clocksource0/current_clocksource
tscCode: Select all
$ cat /sys/kernel/debug/dri/0/amdgpu_firmware_info | grep -i smc
SMC feature version: 0, program: 0, firmware version: 0x00375100 (55.81.0)

