alex.blackbit
Advocate
Joined: 26 Jul 2005
Posts: 2397
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 Posted: Sun Jan 20, 2013 2:16 pm Post subject: make: Implicit linking rule with given executable name |
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Hi,
I want to have a Makefile rule that means | Quote: | Dear make,
please produce an executable called 'foo', it's dependencies is: 'goo.o'.
I will not give you an explicit rule for that, because I don't have special needs.
Kind regards,
-Computeruser |
This seems to be trivial, but my 2 approaches failed: | Code: | $ cat Makefile
foo: goo.o
$ make
cc -c -o goo.o goo.c
$ |
| Code: | $ cat Makefile
foo: goo.c
$ make
make: Nothing to be done for `foo'.
$ |
As already stated I do not want to create an explicit rule for that, the implicit rule for that should be good enough: | Code: | %: %.c
# recipe to execute (built-in):
$(LINK.c) $^ $(LOADLIBES) $(LDLIBS) -o $@ |
Though, when the name of the rule matches the basename of the object file, make does what I intended: | Code: | $ cat Makefile
goo: goo.c
$ make
cc goo.c -o goo
$ |
| Code: | $ cat Makefile
goo: goo.o
$ make
cc -c goo.o goo.c
cc goo.o -o goo
$ |
As it seems I have a kind of misunderstanding about Makefile rules.
Any hints welcome.
Thanks in advance. |
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