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[PATCH] Enabling (more) MSI usage for AMD SB700
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Ant P.
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PostPosted: Fri Dec 28, 2012 6:03 pm    Post subject: Reply with quote

Just applied this patch to zen-sources 3.7.1 and it seems to be working well. I can post an updated diff for that if you'd like.
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_______0
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PostPosted: Fri Dec 28, 2012 6:16 pm    Post subject: Reply with quote

cool, I'd like to try since disabling ohci driver resulted in several USB ports not working anymore :/

What about the timer question??
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_______0
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PostPosted: Tue Jan 08, 2013 1:32 pm    Post subject: Reply with quote

sorry if it's a dumb question, but how to apply the patch? I want to use it.


I am drooling over this :/
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roarinelk
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PostPosted: Tue Jan 08, 2013 5:09 pm    Post subject: Reply with quote

_______0 wrote:
roarinelk wrote:
maudeb wrote:
4 965

...but I still can't see HPET_MSI-edge (BLK_DEV_FD is not set). I'd really like if someone could port this on the kernel tree.


a) it's overrated (APIC timer has a much higher resolution than HPET),
b) you need to set CONFIG_HPET=n AND have a HPET with 3 or more timers for one of the
entries to appear.


this is interesting, how to pick APIC timer?? I don't see it in /sys/bus/clocksource/devices/clocksource0/available_clocksource


go with tsc if it is in there, it's the most precise one (runs with CPU clock).
The APIC timer is the "LOC" line in /proc/interrupts, I *think* it's used for the scheduler


Quote:

And how do you determine HPET is overrated and apic timer is better??


the hpet is an awkward to program 14.something MHz timer in the southbridge;
the apic is the interrupt controller in the cpu which usually runs at bus clock and
raises an irq to the cpu it is attached to (whereas the hpet usually raises global
interrupts to all cpus).


Last edited by roarinelk on Tue Jan 08, 2013 5:12 pm; edited 1 time in total
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roarinelk
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PostPosted: Tue Jan 08, 2013 5:09 pm    Post subject: Reply with quote

_______0 wrote:
sorry if it's a dumb question, but how to apply the patch? I want to use it.


I am drooling over this :/


you should start by reading the wiki sections regarding kernel sources and the patch utility!
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_______0
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PostPosted: Wed Jan 09, 2013 11:17 am    Post subject: Reply with quote

wow, your true!!

Code:
hpet0: 3 comparators, 32-bit 14.318180 MHz counter


compared to:

Code:
tsc: Detected 3110.206 MHz processor


however hpet wins in floating point numbers, hpet "14.318180 MHz" against tsc "3110.206 MHz". Does it mean hpet is more accurate? You know, more decimals (floating point) higher precision, moreover there are THREE hpet's.

roarinelk wrote:
go with tsc if it is in there, it's the most precise one (runs with CPU clock).


According to the wiki http://en.wikipedia.org/wiki/RDTSC TSC has serious drawbacks with synching. And it's not entirely clear late in the paragraph whether the fixes to stabilize the TSC clock can substitute HPET.


roarinelk wrote:
The APIC timer is the "LOC" line in /proc/interrupts, I *think* it's used for the scheduler



The line in /proc/interrupts:
Code:
LOC Local timer interrupts


does not belong exclusively to TSC timer, I am using hpet and there's still activity in there.

So the question remains, HOW DO YOU DETERMINE TSC IS BETTER???

PS: PLZ SEND ME TEH CODEZ!! No seriously, is that hard to copy and paste the command so I can patch this kewl thing immediately??? I am not saying not to RTFM, but in the meantime, while I RTFM, I can have the kernel nicely patched. pls cut and paste here how to patch this. Besides you didn't tell me which wiki to read.
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_______0
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PostPosted: Wed Nov 06, 2013 10:44 pm    Post subject: Reply with quote

does this patch survive kernel 3.12?

thanks.
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PrakashP
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PostPosted: Sun Nov 17, 2013 11:39 am    Post subject: Reply with quote

I'm using the same patch for current git kernel. I works for 3.12, as well. I'm just not sure whether you need to do some manual applying. I just noticed for the git kernel (3.12.0+) the PATA controller won't use an MSI anymore. I'll try to find find out why when I got time.
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zbiggy
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PostPosted: Sun Dec 08, 2013 12:29 am    Post subject: Reply with quote

Hi,

please publish patch for kernel 3.12. These patches published here fails:
Code:

checking file arch/x86/kernel/quirks.c
Hunk #1 succeeded at 497 with fuzz 1 (offset 4 lines).
Hunk #2 FAILED at 509.
1 out of 2 hunks FAILED
checking file drivers/ata/pata_atiixp.c
Hunk #1 FAILED at 262.
1 out of 1 hunk FAILED
checking file drivers/pci/quirks.c
Hunk #1 FAILED at 2665.
1 out of 1 hunk FAILED
checking file drivers/usb/host/ehci-pci.c
Hunk #1 FAILED at 465.
Hunk #2 FAILED at 536.
2 out of 2 hunks FAILED
checking file drivers/usb/host/ohci-pci.c
Hunk #1 succeeded at 28 with fuzz 2 (offset -311 lines).
Hunk #2 FAILED at 412.
1 out of 2 hunks FAILED
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PrakashP
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PostPosted: Fri Dec 13, 2013 10:13 pm    Post subject: Reply with quote

OK, I edited the first post to include the patch against Linux 3.12.5.
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zbiggy
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PostPosted: Wed Jan 22, 2014 6:56 pm    Post subject: Reply with quote

Your patch fails when applied on sources from kernel.org.

So I rewrote it to cleanly apply on kernel.org 3.12 sources.
It also applies on 3.13 sources from kernel.org

What's new:
* added pci ids to enable MSI on AMD Hudson chipsets (ehci usb, ohci usb, hd audio azalia).

Result:
Code:
           CPU0       CPU1       CPU2       CPU3       
  0:         42          0          0          0   IO-APIC-edge      timer
  1:        947        934       1026       1105   IO-APIC-edge      i8042
  7:          1          0          0          0   IO-APIC-edge   
  8:          1          0          0          0   IO-APIC-edge      rtc0
  9:        193        193        201        216   IO-APIC-fasteoi   acpi
 12:      68254      68680      73450      83087   IO-APIC-edge      i8042
 23:          0          0          0          0   IO-APIC-edge      lis3lv02d
 40:          0          0          0          0   PCI-MSI-edge      PCIe PME
 41:          0          0          0          0   PCI-MSI-edge      PCIe PME
 42:          0          0          0          0   PCI-MSI-edge      PCIe PME
 43:       5535       5571       5679       5801   PCI-MSI-edge      ahci
 44:          0          0          0          0   PCI-MSI-edge      xhci_hcd
 45:          0          0          0          0   PCI-MSI-edge      xhci_hcd
 46:          0          0          0          0   PCI-MSI-edge      xhci_hcd
 47:          0          0          0          0   PCI-MSI-edge      xhci_hcd
 48:          0          0          0          0   PCI-MSI-edge      xhci_hcd
 49:          0          0          0          0   PCI-MSI-edge      xhci_hcd
 50:          0          0          0          0   PCI-MSI-edge      xhci_hcd
 51:          0          0          0          0   PCI-MSI-edge      xhci_hcd
 52:          0          0          0          0   PCI-MSI-edge      xhci_hcd
 53:          0          0          0          0   PCI-MSI-edge      xhci_hcd
 54:          7          5          6         10   PCI-MSI-edge      ehci_hcd:usb5
 55:          0          0          0          0   PCI-MSI-edge      ehci_hcd:usb6
 56:         26         21         24         25   PCI-MSI-edge      snd_hda_intel
 57:          0          1          0          0   PCI-MSI-edge      ohci_hcd:usb7
 58:       2368       2470       2605       3186   PCI-MSI-edge      enp1s0
 59:          1          0          0          0   PCI-MSI-edge      ohci_hcd:usb8
 60:          0          1          0          0   PCI-MSI-edge      ohci_hcd:usb9
 61:        633        635        637        656   PCI-MSI-edge      snd_hda_intel
 63:      13962      13958      15012      17308   PCI-MSI-edge      radeon


Patch for kernel.org 3.12/3.13
Code:

--- arch/x86/kernel/quirks.c   2013-11-04 00:41:51.000000000 +0100
+++ arch/x86/kernel/quirks.c   2013-12-24 03:09:11.000000000 +0100
@@ -497,6 +497,8 @@
    }
 }
 
+/* XXX: should add EPP/ECP parport as well.. */
+#if defined(CONFIG_BLK_DEV_FD) ||  defined(CONFIG_BLK_DEV_FD_MODULE)
 /*
  * HPET MSI on some boards (ATI SB700/SB800) has side effect on
  * floppy DMA. Disable HPET MSI on such platforms.
@@ -511,6 +513,7 @@
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
           force_disable_hpet_msi);
+#endif
 
 #endif
 
--- drivers/ata/pata_atiixp.c   2013-11-04 00:41:51.000000000 +0100
+++ drivers/ata/pata_atiixp.c   2013-12-24 03:09:06.000000000 +0100
@@ -278,7 +278,15 @@
       .port_ops = &atiixp_port_ops
    };
    const struct ata_port_info *ppi[] = { &info, &info };
+        u8 tmp8, mask;
 
+        pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
+        mask = (1 << 2) | (1 << 0);
+   
+        /* Both channels in native mode? */
+        if ((tmp8 & mask) == mask)
+           pci_enable_msi(pdev);
+   
    return ata_pci_bmdma_init_one(pdev, ppi, &atiixp_sht, NULL,
                   ATA_HOST_PARALLEL_SCAN);
 }
--- drivers/pci/quirks.c   2013-11-04 00:41:51.000000000 +0100
+++ drivers/pci/quirks.c   2013-12-24 03:41:13.000000000 +0100
@@ -2581,16 +2581,44 @@
          PCI_DEVICE_ID_TIGON3_5715S,
          quirk_msi_intx_disable_bug);
 
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
-         quirk_msi_intx_disable_ati_bug);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
-         quirk_msi_intx_disable_ati_bug);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
-         quirk_msi_intx_disable_ati_bug);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
-         quirk_msi_intx_disable_ati_bug);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
-         quirk_msi_intx_disable_ati_bug);
+/* Enable MSI capability on SB7x0 SATA */
+static void quirk_amd_sb700_sata_enable_msi_capability(struct pci_dev *dev)
+{
+   u8 tmp;
+
+   pci_read_config_byte(dev, 0x34, &tmp);
+   
+   /* Is D3 enabled or MSI disabled? */
+   if (tmp != 0x50) {
+      pci_read_config_byte(dev, 0x40, &tmp);
+      pci_write_config_byte(dev, 0x40, tmp|1);
+
+      /* Set next pointer to MSI cap ignoring power management cap, see RPR 7.11 */
+      pci_write_config_byte(dev, 0x34, 0x50);
+
+      pci_write_config_byte(dev, 0x40, tmp);
+      dev_info(&dev->dev, "Enabled SATA MSI capability and disabled D3 power management capability\n");
+   }
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4390, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4390, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4391, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4391, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4392, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4392, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4393, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4393, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4394, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4394, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, quirk_msi_intx_disable_ati_bug);
 
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
          quirk_msi_intx_disable_bug);
@@ -2599,6 +2627,113 @@
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
          quirk_msi_intx_disable_bug);
 
+/* Enable MSI capability on SB7x0 PCIB */
+static void quirk_amd_sb700_pcib_enable_msi_capability(struct pci_dev *dev)
+{
+   u8 tmp;
+
+   pci_read_config_byte(dev, 0x40, &tmp);
+   
+   /* Is MSI disabled ? */
+   if ((tmp & (1 << 3)) == 0) {
+      pci_write_config_byte(dev, 0x40, tmp | (1 << 3));
+      dev_info(&dev->dev, "Enabled PCIB MSI capability\n");
+   }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4384, quirk_amd_sb700_pcib_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4384, quirk_amd_sb700_pcib_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4384, quirk_msi_intx_disable_ati_bug);
+
+/* Enable MSI capability on SB7x0/FCH Azalia */
+static void quirk_amd_sb700_azalia_enable_msi_capability(struct pci_dev *dev)
+{
+   u8 tmp;
+
+   pci_read_config_byte(dev, 0x45, &tmp);
+   
+   /* Is MSI disabled ? */
+   if ((tmp & 1) == 0) {
+      pci_write_config_byte(dev, 0x45, tmp | 1);
+      dev_info(&dev->dev, "Enabled Azalia MSI capability\n");
+   }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4383, quirk_amd_sb700_azalia_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4383, quirk_amd_sb700_azalia_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4383, quirk_msi_intx_disable_ati_bug);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x780d, quirk_amd_sb700_azalia_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x780d, quirk_amd_sb700_azalia_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x780d, quirk_msi_intx_disable_ati_bug);
+
+/* Enable MSI capability on SB7x0/FCH OHCI */
+static void quirk_amd_sb700_ohci_enable_msi_capability(struct pci_dev *dev)
+{
+   u8 tmp;
+
+   pci_read_config_byte(dev, 0x41, &tmp);
+   
+   /* Is MSI disabled ? */
+   if ((tmp & 3) != 0) {
+      pci_write_config_byte(dev, 0x41, tmp & ~3);
+      dev_info(&dev->dev, "Enabled OHCI0/1 MSI capability\n");
+   }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4397, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4397, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4397, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4398, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4398, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4398, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4399, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4399, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4399, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7807, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7807, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7807, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7809, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7809, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7809, quirk_msi_intx_disable_ati_bug);
+
+/* Enable MSI capability on SB7x0/FCH EHCI */
+static void quirk_amd_sb700_ehci_enable_msi_capability(struct pci_dev *dev)
+{
+   u8 tmp;
+
+   pci_read_config_byte(dev, 0x50, &tmp);
+   
+   /* Is MSI disabled ? */
+   if ((tmp & (1 << 6)) != 0) {
+      pci_write_config_byte(dev, 0x50, tmp & ~(1 << 6));
+      dev_info(&dev->dev, "Enabled EHCI MSI capability\n");
+   }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4396, quirk_amd_sb700_ehci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4396, quirk_amd_sb700_ehci_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4396, quirk_msi_intx_disable_ati_bug);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7808, quirk_amd_sb700_ehci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7808, quirk_amd_sb700_ehci_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, quirk_msi_intx_disable_ati_bug);
+
+static void quirk_amd_ide_native_mode(struct pci_dev *pdev)
+{
+   /* set SBX00/Hudson-2 IDE to native mode */
+   const u8 mask = 1 | (1 << 2);
+   u8 tmp;
+
+   pci_read_config_byte(pdev, 0x9, &tmp);
+   if ((tmp & mask) != mask) {
+      pci_write_config_byte(pdev, 0x9, tmp | mask);
+      dev_info(&pdev->dev, "set both IDE channels to native mode\n");
+   }
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x439c, quirk_amd_ide_native_mode);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x439c, quirk_amd_ide_native_mode);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x439c, quirk_msi_intx_disable_ati_bug);
+
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
          quirk_msi_intx_disable_bug);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
--- drivers/usb/host/ehci-pci.c   2013-11-04 00:41:51.000000000 +0100
+++ drivers/usb/host/ehci-pci.c   2013-12-24 03:08:53.000000000 +0100
@@ -352,12 +352,19 @@
 };
 MODULE_DEVICE_TABLE(pci, pci_ids);
 
+static int ehci_hcd_pci_probe(struct pci_dev *dev,
+                  const struct pci_device_id *id)
+{
+   pci_enable_msi(dev);
+   return usb_hcd_pci_probe(dev, id);
+}
+
 /* pci driver glue; this is a "new style" PCI driver module */
 static struct pci_driver ehci_pci_driver = {
    .name =      (char *) hcd_name,
    .id_table =   pci_ids,
 
-   .probe =   usb_hcd_pci_probe,
+   .probe =   ehci_hcd_pci_probe,
    .remove =   usb_hcd_pci_remove,
    .shutdown =    usb_hcd_pci_shutdown,
 
--- drivers/usb/host/ohci-pci.c   2013-11-04 00:41:51.000000000 +0100
+++ drivers/usb/host/ohci-pci.c   2013-12-24 03:09:01.000000000 +0100
@@ -27,7 +27,12 @@
 #define DRIVER_DESC "OHCI PCI platform driver"
 
 static const char hcd_name[] = "ohci-pci";
-
+static int ohci_hcd_pci_probe(struct pci_dev *dev,
+                  const struct pci_device_id *id)
+{
+   pci_enable_msi(dev);
+   return usb_hcd_pci_probe(dev, id);
+}
 
 /*-------------------------------------------------------------------------*/
 
@@ -285,7 +290,7 @@
    .name =      (char *) hcd_name,
    .id_table =   pci_ids,
 
-   .probe =   usb_hcd_pci_probe,
+   .probe =   ohci_hcd_pci_probe,
    .remove =   usb_hcd_pci_remove,
    .shutdown =   usb_hcd_pci_shutdown,
 

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Last edited by zbiggy on Sun Feb 02, 2014 12:29 pm; edited 1 time in total
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PrakashP
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PostPosted: Thu Jan 23, 2014 5:18 pm    Post subject: Reply with quote

Have you checked, whether you really need the quirk_msi_intx_disable_ati_bug for your newer chipset? Ie. does this line alone work for your OHCI controller:

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7807, quirk_amd_sb700_ohci_enable_msi_capability);
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Zentoo
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PostPosted: Mon Jan 27, 2014 12:05 pm    Post subject: Reply with quote

Looking to enable MSI usage on my USB ports on an intel X58 board, I've found your patch really interesting.

Is your patch really specific to AMD chipset ?

Actually, I got everything using MSI except:
- snd_emu10k1
- i801_smbus
- ehci_hcd:usb*
- uhci_hcd:usb*

I would like to get MSI for snd_emu10k1 in order that the soundcard doesn't share the same IRQ than USB port.

So your point of view on this point interest me really.
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roarinelk
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PostPosted: Tue Jan 28, 2014 7:14 am    Post subject: Reply with quote

Zentoo wrote:
Looking to enable MSI usage on my USB ports on an intel X58 board, I've found your patch really interesting.

Is your patch really specific to AMD chipset ?

Actually, I got everything using MSI except:
- snd_emu10k1
- i801_smbus
- ehci_hcd:usb*
- uhci_hcd:usb*

I would like to get MSI for snd_emu10k1 in order that the soundcard doesn't share the same IRQ than USB port.


yes it's AMD-specific. The emu10k1 is a pure PCI card, right? I don't think it even supports MSI. Same goes for the i801_smbus.
I'm not sure if the intel usb blocks support msi; if they do it certainly isn't advertised in lspci.
you may need to find some programming manuals for the x58 to be able to reveal the MSI capability.

finally, irq sharing isn't bad, it's a feature of pci. Do you have any problems with sound and usb?
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PostPosted: Sun Feb 02, 2014 11:29 am    Post subject: Reply with quote

Zentoo wrote:
Looking to enable MSI usage on my USB ports on an intel X58 board, I've found your patch really interesting.

Is your patch really specific to AMD chipset ?

Actually, I got everything using MSI except:
- snd_emu10k1
- i801_smbus
- ehci_hcd:usb*
- uhci_hcd:usb*

I would like to get MSI for snd_emu10k1 in order that the soundcard doesn't share the same IRQ than USB port.

So your point of view on this point interest me really.


Yes. It is AMD specific and not for all AMD chipsets. For sure it is for AMD SB7xx and recently patch is updated for my AMD Hudson A76M in my laptop.

snd_emu10k1 driver is used for EMU10K 1/2/2.5 chipsets: K1 - SB Live!/K2- Audigy1/K2.5 - Audigy 2 ZS or 4. All these chipsets are native PCI devices. Even later X-FI known as EMU20K1 was still PCI device. Later they made X-FI on PCI-E bus (EMU20K2) by adding RISC CPU on board to translate and buffer PCI-E->PCI transactions because X-FI remains native PCI chip.
According to wikipedia: http://en.wikipedia.org/wiki/Message_Signaled_Interrupts MSI formally was introduced in PCI 2.2 and MSI-X in PCI 3.0 both as option. Nobody I know implemented this in PCI chips because implementation is difficult - that is why it was not used in PCI. In PCI-E specification MSI is required not optional. So chip designers have no choice - they have to implement it.
You can search for EMU10K programming docs on the net to check if it mentions MSI interrupts. If yes we can try to activate it. But as described above it is doubtful they have it.

i801_smbus ehci_hcd uhci_hcd - These are still PCI devices. Intel have programming docs for it's every chipset publicly available. In previous year I have checked Intel programming docs for Sandy Bridge/Ivy Bridge and Haswell. Still no MSI for ehci usb - uhci was dropped from design. I have checked also docs for NM10 chipset in my Atom netbook. It has EHCI/UHCI - no luck.
I think Intel will never add msi to UHCI/EHCI because they are going to be removed. USB 3.0 - xhci has MSI as native PCIe device and will replace legacy UHCI/EHCI. They are only waiting for WinXP to die out on April this year to remove old usb controllers and leave only xhci.
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Last edited by zbiggy on Sun Feb 02, 2014 12:29 pm; edited 1 time in total
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PostPosted: Sun Feb 02, 2014 12:11 pm    Post subject: Reply with quote

PrakashP wrote:
Have you checked, whether you really need the quirk_msi_intx_disable_ati_bug for your newer chipset? Ie. does this line alone work for your OHCI controller:

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7807, quirk_amd_sb700_ohci_enable_msi_capability);


Good point. Here is cumulative patch with inx removed for Hudson (azalia HD audio, ehci/ohci usb = everything) . Works for me since implemented it few weeks ago.
TODO: MSI are enabled for Hudson only for devices I use. For example switching ahci to ide/raid mode may require updating this patch for IDE/raid mode as pci ids and hdd controllers will change.
Will look at it if find time.

Code:

--- arch/x86/kernel/quirks.c   2013-11-04 00:41:51.000000000 +0100
+++ arch/x86/kernel/quirks.c   2013-12-24 03:09:11.000000000 +0100
@@ -497,6 +497,8 @@
    }
 }
 
+/* XXX: should add EPP/ECP parport as well.. */
+#if defined(CONFIG_BLK_DEV_FD) ||  defined(CONFIG_BLK_DEV_FD_MODULE)
 /*
  * HPET MSI on some boards (ATI SB700/SB800) has side effect on
  * floppy DMA. Disable HPET MSI on such platforms.
@@ -511,6 +513,7 @@
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
           force_disable_hpet_msi);
+#endif
 
 #endif
 
--- drivers/ata/pata_atiixp.c   2013-11-04 00:41:51.000000000 +0100
+++ drivers/ata/pata_atiixp.c   2013-12-24 03:09:06.000000000 +0100
@@ -278,7 +278,15 @@
       .port_ops = &atiixp_port_ops
    };
    const struct ata_port_info *ppi[] = { &info, &info };
+        u8 tmp8, mask;
 
+        pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
+        mask = (1 << 2) | (1 << 0);
+   
+        /* Both channels in native mode? */
+        if ((tmp8 & mask) == mask)
+           pci_enable_msi(pdev);
+   
    return ata_pci_bmdma_init_one(pdev, ppi, &atiixp_sht, NULL,
                   ATA_HOST_PARALLEL_SCAN);
 }
--- drivers/pci/quirks.c   2013-11-04 00:41:51.000000000 +0100
+++ drivers/pci/quirks.c   2013-12-24 03:41:13.000000000 +0100
@@ -2581,16 +2581,44 @@
          PCI_DEVICE_ID_TIGON3_5715S,
          quirk_msi_intx_disable_bug);
 
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
-         quirk_msi_intx_disable_ati_bug);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
-         quirk_msi_intx_disable_ati_bug);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
-         quirk_msi_intx_disable_ati_bug);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
-         quirk_msi_intx_disable_ati_bug);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
-         quirk_msi_intx_disable_ati_bug);
+/* Enable MSI capability on SB7x0 SATA */
+static void quirk_amd_sb700_sata_enable_msi_capability(struct pci_dev *dev)
+{
+   u8 tmp;
+
+   pci_read_config_byte(dev, 0x34, &tmp);
+   
+   /* Is D3 enabled or MSI disabled? */
+   if (tmp != 0x50) {
+      pci_read_config_byte(dev, 0x40, &tmp);
+      pci_write_config_byte(dev, 0x40, tmp|1);
+
+      /* Set next pointer to MSI cap ignoring power management cap, see RPR 7.11 */
+      pci_write_config_byte(dev, 0x34, 0x50);
+
+      pci_write_config_byte(dev, 0x40, tmp);
+      dev_info(&dev->dev, "Enabled SATA MSI capability and disabled D3 power management capability\n");
+   }
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4390, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4390, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4391, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4391, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4392, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4392, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4393, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4393, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4394, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4394, quirk_amd_sb700_sata_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, quirk_msi_intx_disable_ati_bug);
 
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
          quirk_msi_intx_disable_bug);
@@ -2599,6 +2627,113 @@
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
          quirk_msi_intx_disable_bug);
 
+/* Enable MSI capability on SB7x0 PCIB */
+static void quirk_amd_sb700_pcib_enable_msi_capability(struct pci_dev *dev)
+{
+   u8 tmp;
+
+   pci_read_config_byte(dev, 0x40, &tmp);
+   
+   /* Is MSI disabled ? */
+   if ((tmp & (1 << 3)) == 0) {
+      pci_write_config_byte(dev, 0x40, tmp | (1 << 3));
+      dev_info(&dev->dev, "Enabled PCIB MSI capability\n");
+   }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4384, quirk_amd_sb700_pcib_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4384, quirk_amd_sb700_pcib_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4384, quirk_msi_intx_disable_ati_bug);
+
+/* Enable MSI capability on SB7x0/FCH Azalia */
+static void quirk_amd_sb700_azalia_enable_msi_capability(struct pci_dev *dev)
+{
+   u8 tmp;
+
+   pci_read_config_byte(dev, 0x45, &tmp);
+   
+   /* Is MSI disabled ? */
+   if ((tmp & 1) == 0) {
+      pci_write_config_byte(dev, 0x45, tmp | 1);
+      dev_info(&dev->dev, "Enabled Azalia MSI capability\n");
+   }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4383, quirk_amd_sb700_azalia_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4383, quirk_amd_sb700_azalia_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4383, quirk_msi_intx_disable_ati_bug);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x780d, quirk_amd_sb700_azalia_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x780d, quirk_amd_sb700_azalia_enable_msi_capability);
+
+
+/* Enable MSI capability on SB7x0/FCH OHCI */
+static void quirk_amd_sb700_ohci_enable_msi_capability(struct pci_dev *dev)
+{
+   u8 tmp;
+
+   pci_read_config_byte(dev, 0x41, &tmp);
+   
+   /* Is MSI disabled ? */
+   if ((tmp & 3) != 0) {
+      pci_write_config_byte(dev, 0x41, tmp & ~3);
+      dev_info(&dev->dev, "Enabled OHCI0/1 MSI capability\n");
+   }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4397, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4397, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4397, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4398, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4398, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4398, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4399, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4399, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4399, quirk_msi_intx_disable_ati_bug);
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7807, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7807, quirk_amd_sb700_ohci_enable_msi_capability);
+
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7809, quirk_amd_sb700_ohci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7809, quirk_amd_sb700_ohci_enable_msi_capability);
+
+
+/* Enable MSI capability on SB7x0/FCH EHCI */
+static void quirk_amd_sb700_ehci_enable_msi_capability(struct pci_dev *dev)
+{
+   u8 tmp;
+
+   pci_read_config_byte(dev, 0x50, &tmp);
+   
+   /* Is MSI disabled ? */
+   if ((tmp & (1 << 6)) != 0) {
+      pci_write_config_byte(dev, 0x50, tmp & ~(1 << 6));
+      dev_info(&dev->dev, "Enabled EHCI MSI capability\n");
+   }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4396, quirk_amd_sb700_ehci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x4396, quirk_amd_sb700_ehci_enable_msi_capability);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4396, quirk_msi_intx_disable_ati_bug);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7808, quirk_amd_sb700_ehci_enable_msi_capability);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7808, quirk_amd_sb700_ehci_enable_msi_capability);
+
+
+static void quirk_amd_ide_native_mode(struct pci_dev *pdev)
+{
+   /* set SBX00/Hudson-2 IDE to native mode */
+   const u8 mask = 1 | (1 << 2);
+   u8 tmp;
+
+   pci_read_config_byte(pdev, 0x9, &tmp);
+   if ((tmp & mask) != mask) {
+      pci_write_config_byte(pdev, 0x9, tmp | mask);
+      dev_info(&pdev->dev, "set both IDE channels to native mode\n");
+   }
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x439c, quirk_amd_ide_native_mode);
+DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, 0x439c, quirk_amd_ide_native_mode);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x439c, quirk_msi_intx_disable_ati_bug);
+
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
          quirk_msi_intx_disable_bug);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
--- drivers/usb/host/ehci-pci.c   2013-11-04 00:41:51.000000000 +0100
+++ drivers/usb/host/ehci-pci.c   2013-12-24 03:08:53.000000000 +0100
@@ -352,12 +352,19 @@
 };
 MODULE_DEVICE_TABLE(pci, pci_ids);
 
+static int ehci_hcd_pci_probe(struct pci_dev *dev,
+                  const struct pci_device_id *id)
+{
+   pci_enable_msi(dev);
+   return usb_hcd_pci_probe(dev, id);
+}
+
 /* pci driver glue; this is a "new style" PCI driver module */
 static struct pci_driver ehci_pci_driver = {
    .name =      (char *) hcd_name,
    .id_table =   pci_ids,
 
-   .probe =   usb_hcd_pci_probe,
+   .probe =   ehci_hcd_pci_probe,
    .remove =   usb_hcd_pci_remove,
    .shutdown =    usb_hcd_pci_shutdown,
 
--- drivers/usb/host/ohci-pci.c   2013-11-04 00:41:51.000000000 +0100
+++ drivers/usb/host/ohci-pci.c   2013-12-24 03:09:01.000000000 +0100
@@ -27,7 +27,12 @@
 #define DRIVER_DESC "OHCI PCI platform driver"
 
 static const char hcd_name[] = "ohci-pci";
-
+static int ohci_hcd_pci_probe(struct pci_dev *dev,
+                  const struct pci_device_id *id)
+{
+   pci_enable_msi(dev);
+   return usb_hcd_pci_probe(dev, id);
+}
 
 /*-------------------------------------------------------------------------*/
 
@@ -285,7 +290,7 @@
    .name =      (char *) hcd_name,
    .id_table =   pci_ids,
 
-   .probe =   usb_hcd_pci_probe,
+   .probe =   ohci_hcd_pci_probe,
    .remove =   usb_hcd_pci_remove,
    .shutdown =   usb_hcd_pci_shutdown,
 

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