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whitenoise Tux's lil' helper
Joined: 24 May 2002 Posts: 88 Location: Genoa , Italy
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Posted: Tue Jun 04, 2002 4:00 pm Post subject: Athlon-mp flags and thunderbird cpu. |
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I'm running a dual rig with 2 thunderbirds. May i have some problems if i use gcc3.1 with athlon-mp flags?
The only difference between MP and TB is the organic/ceramic package. (I supposed).
Gio _________________ Gentoo Linux running on TyanMPX, 2* 1600+ AthlonMP, 4*256 Mb Crucial Registered DDR, Adaptec 29160, 2*18GB Fujitsu SCSI 10krpm, Nvidia geforce, SB Live!, 3com905TX, Zyxel 645R. |
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Niek Apprentice
Joined: 14 May 2002 Posts: 236 Location: Houten, The Netherlands
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Forge Tux's lil' helper
Joined: 20 Jun 2002 Posts: 125 Location: KOP, PA, USA
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Posted: Tue Jun 25, 2002 3:19 am Post subject: |
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Tbird = no prefetch, no SSE, missing some of the newest 3Dnow! features, no cache coherency protocol support.
More than just ceramic/organic. |
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tsuru Tux's lil' helper
Joined: 19 Apr 2002 Posts: 99 Location: Nashville, Tennessee, USA
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Posted: Tue Jun 25, 2002 2:49 pm Post subject: |
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hmmm... I wonder about a the Athlon MP 1800+ and above chips then... I was under the impression that those models were the same as XP.
I hope the athlon-mp flag helps my current compile problems to say the least |
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Forge Tux's lil' helper
Joined: 20 Jun 2002 Posts: 125 Location: KOP, PA, USA
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Posted: Tue Jun 25, 2002 3:10 pm Post subject: |
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I direct you to another post on another board where I laid out the K7* series very nicely, with a little help from sandpile.
http://forums.2cpu.com/showthread.php?s=&postid=144488#post144488
The original Athlon Classic core was basically a super-P2 with 3Dnow. It was die shrunk (.25 -> .1 and tweaked (minor heat reduction due to relayout due to cache moving on die) and had the cache moved on die (and cut from 512K to 256K), but no real functionality improvements, at least from the compiler's point of view. (Slot - K7, K75) (Socket- Thunderbird, Spitfire)
Speculative prefetch, full SSE, additional 3Dnow opcodes, and a cache coherency protocol were added. (Palomino, Morgan)
The die got shrunk again (.13 micron), and Durons went the way of the dodo. No functionality changes. (Thoroughbred)
Basically, there are two types of Athlons.
Older, Super Pentium II-types with 3Dnow and incomplete SSE.
Newer, Super Pentium III-types with 3Dnow Professional and complete SSE.
The Athlon/Duron are the former, the Athlon MP/XP/4 and Durons >=1GHz are the latter.
Any points I missed? Anything still unclear? |
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Forge Tux's lil' helper
Joined: 20 Jun 2002 Posts: 125 Location: KOP, PA, USA
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Posted: Tue Jun 25, 2002 3:22 pm Post subject: |
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Meh. Forgot to put the point in there. The following is educated speculation, do not reference when designing heart/lung machines.
-march=athlon = older 512K offdie super-P2s, but should work decently on any K7
-march=athlon-tbird = 256K ondie cache K7s, otherwise identical to above
-march=athlon-xp = same as above, use SSE, use newer 3Dnow, use prefetch
-march=athlon-mp = same, use cache coherency protocol (for SMP only, but is present on XPs and Athlon 4s)
-march=athlon-4 = same as XP, plus enable PowerNow power/frequency management
(The MP/XP/4 differences are more speculation than not. The cores are physically 100% identical, no idea why GCC would specify them all separtely, except maybe for cosmetic reasons only, while aliasing all three to one profile internally. *shrug*) |
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snowsquirrel n00b
Joined: 02 Jul 2002 Posts: 41 Location: Lunenburg, NS, Canada
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Posted: Tue Jul 02, 2002 10:09 pm Post subject: |
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Forge:
I have a dual 1GHz Duron system. They were early realeases of the Durons, so SMP was enabled (BIOS and /dev/cupinfo both see "Durons MP's" !). Do you think that the -march=athlon-mp would work in my system? |
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dshi n00b
Joined: 03 Jul 2002 Posts: 1
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Posted: Wed Jul 03, 2002 2:45 am Post subject: Dual Durons |
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snowsquirrel:
I recently put dual durons (1.3) on TigerMPX. Compiled the 1.3b with athlon-mp. System runs fine with no problems so far. Yes they are identified as Duron MP. |
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Forge Tux's lil' helper
Joined: 20 Jun 2002 Posts: 125 Location: KOP, PA, USA
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Posted: Wed Jul 03, 2002 6:02 pm Post subject: |
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The Morgan core used for the 1GHz+ Durons is functionally identical to the Palomino core, only the cache size differs.
The cores are IDed as Duron MPs because AMD was going to make MP certified Durons, but decided not to. My Athlon XPs are IDed as Athlon MPs in the BIOS. The only way a system can tell MPs and XPs apart is a L5 bridge on the chip surface, or whether or not there are 2 or more CPUs in the system.
Nothing in the CPU itself is different, just the certification.
Basically, you should have no problem using athlon-mp, especially since nobody (that's talking) is sure what the diff between the athlon compiler options are. |
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